| /* |
| * Copyright (C) 2024 Apple Inc. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * 1. Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * |
| * THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' AND ANY |
| * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #pragma once |
| |
| #include <wtf/Compiler.h> |
| #include <wtf/Platform.h> |
| |
| #if CPU(ARM64) && OS(DARWIN) |
| |
| // Use the built-in precompiled module to avoid parsing ~170k LoC |
| // in every translation unit. |
| #include <arm_neon.h> |
| |
| // Declare simde-compatible symbols because simde is our cross-platform |
| // abstraction layer for SIMD. |
| |
| using simde_float16x4_t = float16x4_t; |
| using simde_float16x4x2_t = float16x4x2_t; |
| using simde_float16x4x3_t = float16x4x3_t; |
| using simde_float16x4x4_t = float16x4x4_t; |
| using simde_float16x8_t = float16x8_t; |
| using simde_float16x8x2_t = float16x8x2_t; |
| using simde_float16x8x3_t = float16x8x3_t; |
| using simde_float16x8x4_t = float16x8x4_t; |
| using simde_float32x2_t = float32x2_t; |
| using simde_float32x2x2_t = float32x2x2_t; |
| using simde_float32x2x3_t = float32x2x3_t; |
| using simde_float32x2x4_t = float32x2x4_t; |
| using simde_float32x4_t = float32x4_t; |
| using simde_float32x4x2_t = float32x4x2_t; |
| using simde_float32x4x3_t = float32x4x3_t; |
| using simde_float32x4x4_t = float32x4x4_t; |
| using simde_float64x1_t = float64x1_t; |
| using simde_float64x1x2_t = float64x1x2_t; |
| using simde_float64x1x3_t = float64x1x3_t; |
| using simde_float64x1x4_t = float64x1x4_t; |
| using simde_float64x2_t = float64x2_t; |
| using simde_float64x2x2_t = float64x2x2_t; |
| using simde_float64x2x3_t = float64x2x3_t; |
| using simde_float64x2x4_t = float64x2x4_t; |
| using simde_int16x4_t = int16x4_t; |
| using simde_int16x4x2_t = int16x4x2_t; |
| using simde_int16x4x3_t = int16x4x3_t; |
| using simde_int16x4x4_t = int16x4x4_t; |
| using simde_int16x8_t = int16x8_t; |
| using simde_int16x8x2_t = int16x8x2_t; |
| using simde_int16x8x3_t = int16x8x3_t; |
| using simde_int16x8x4_t = int16x8x4_t; |
| using simde_int32x2_t = int32x2_t; |
| using simde_int32x2x2_t = int32x2x2_t; |
| using simde_int32x2x3_t = int32x2x3_t; |
| using simde_int32x2x4_t = int32x2x4_t; |
| using simde_int32x4_t = int32x4_t; |
| using simde_int32x4x2_t = int32x4x2_t; |
| using simde_int32x4x3_t = int32x4x3_t; |
| using simde_int32x4x4_t = int32x4x4_t; |
| using simde_int64x1_t = int64x1_t; |
| using simde_int64x1x2_t = int64x1x2_t; |
| using simde_int64x1x3_t = int64x1x3_t; |
| using simde_int64x1x4_t = int64x1x4_t; |
| using simde_int64x2_t = int64x2_t; |
| using simde_int64x2x2_t = int64x2x2_t; |
| using simde_int64x2x3_t = int64x2x3_t; |
| using simde_int64x2x4_t = int64x2x4_t; |
| using simde_int8x16_t = int8x16_t; |
| using simde_int8x16x2_t = int8x16x2_t; |
| using simde_int8x16x3_t = int8x16x3_t; |
| using simde_int8x16x4_t = int8x16x4_t; |
| using simde_int8x8_t = int8x8_t; |
| using simde_int8x8x2_t = int8x8x2_t; |
| using simde_int8x8x3_t = int8x8x3_t; |
| using simde_int8x8x4_t = int8x8x4_t; |
| using simde_poly16x4_t = poly16x4_t; |
| using simde_poly16x4x2_t = poly16x4x2_t; |
| using simde_poly16x4x3_t = poly16x4x3_t; |
| using simde_poly16x4x4_t = poly16x4x4_t; |
| using simde_poly16x8_t = poly16x8_t; |
| using simde_poly16x8x2_t = poly16x8x2_t; |
| using simde_poly16x8x3_t = poly16x8x3_t; |
| using simde_poly16x8x4_t = poly16x8x4_t; |
| using simde_poly64x1_t = poly64x1_t; |
| using simde_poly64x1x2_t = poly64x1x2_t; |
| using simde_poly64x1x3_t = poly64x1x3_t; |
| using simde_poly64x1x4_t = poly64x1x4_t; |
| using simde_poly64x2_t = poly64x2_t; |
| using simde_poly64x2x2_t = poly64x2x2_t; |
| using simde_poly64x2x3_t = poly64x2x3_t; |
| using simde_poly64x2x4_t = poly64x2x4_t; |
| using simde_poly8x16_t = poly8x16_t; |
| using simde_poly8x16x2_t = poly8x16x2_t; |
| using simde_poly8x16x3_t = poly8x16x3_t; |
| using simde_poly8x16x4_t = poly8x16x4_t; |
| using simde_poly8x8_t = poly8x8_t; |
| using simde_poly8x8x2_t = poly8x8x2_t; |
| using simde_poly8x8x3_t = poly8x8x3_t; |
| using simde_poly8x8x4_t = poly8x8x4_t; |
| using simde_uint16x4_t = uint16x4_t; |
| using simde_uint16x4x2_t = uint16x4x2_t; |
| using simde_uint16x4x3_t = uint16x4x3_t; |
| using simde_uint16x4x4_t = uint16x4x4_t; |
| using simde_uint16x8_t = uint16x8_t; |
| using simde_uint16x8x2_t = uint16x8x2_t; |
| using simde_uint16x8x3_t = uint16x8x3_t; |
| using simde_uint16x8x4_t = uint16x8x4_t; |
| using simde_uint32x2_t = uint32x2_t; |
| using simde_uint32x2x2_t = uint32x2x2_t; |
| using simde_uint32x2x3_t = uint32x2x3_t; |
| using simde_uint32x2x4_t = uint32x2x4_t; |
| using simde_uint32x4_t = uint32x4_t; |
| using simde_uint32x4x2_t = uint32x4x2_t; |
| using simde_uint32x4x3_t = uint32x4x3_t; |
| using simde_uint32x4x4_t = uint32x4x4_t; |
| using simde_uint64x1_t = uint64x1_t; |
| using simde_uint64x1x2_t = uint64x1x2_t; |
| using simde_uint64x1x3_t = uint64x1x3_t; |
| using simde_uint64x1x4_t = uint64x1x4_t; |
| using simde_uint64x2_t = uint64x2_t; |
| using simde_uint64x2x2_t = uint64x2x2_t; |
| using simde_uint64x2x3_t = uint64x2x3_t; |
| using simde_uint64x2x4_t = uint64x2x4_t; |
| using simde_uint8x16_t = uint8x16_t; |
| using simde_uint8x16x2_t = uint8x16x2_t; |
| using simde_uint8x16x3_t = uint8x16x3_t; |
| using simde_uint8x16x4_t = uint8x16x4_t; |
| using simde_uint8x8_t = uint8x8_t; |
| using simde_uint8x8x2_t = uint8x8x2_t; |
| using simde_uint8x8x3_t = uint8x8x3_t; |
| using simde_uint8x8x4_t = uint8x8x4_t; |
| |
| #define simde_vaba_s16 vaba_s16 |
| #define simde_vaba_s32 vaba_s32 |
| #define simde_vaba_s8 vaba_s8 |
| #define simde_vaba_u16 vaba_u16 |
| #define simde_vaba_u32 vaba_u32 |
| #define simde_vaba_u8 vaba_u8 |
| #define simde_vabal_high_s16 vabal_high_s16 |
| #define simde_vabal_high_s32 vabal_high_s32 |
| #define simde_vabal_high_s8 vabal_high_s8 |
| #define simde_vabal_high_u16 vabal_high_u16 |
| #define simde_vabal_high_u32 vabal_high_u32 |
| #define simde_vabal_high_u8 vabal_high_u8 |
| #define simde_vabal_s16 vabal_s16 |
| #define simde_vabal_s32 vabal_s32 |
| #define simde_vabal_s8 vabal_s8 |
| #define simde_vabal_u16 vabal_u16 |
| #define simde_vabal_u32 vabal_u32 |
| #define simde_vabal_u8 vabal_u8 |
| #define simde_vabaq_s16 vabaq_s16 |
| #define simde_vabaq_s32 vabaq_s32 |
| #define simde_vabaq_s8 vabaq_s8 |
| #define simde_vabaq_u16 vabaq_u16 |
| #define simde_vabaq_u32 vabaq_u32 |
| #define simde_vabaq_u8 vabaq_u8 |
| #define simde_vabd_f16 vabd_f16 |
| #define simde_vabd_f32 vabd_f32 |
| #define simde_vabd_f64 vabd_f64 |
| #define simde_vabd_s16 vabd_s16 |
| #define simde_vabd_s32 vabd_s32 |
| #define simde_vabd_s8 vabd_s8 |
| #define simde_vabd_u16 vabd_u16 |
| #define simde_vabd_u32 vabd_u32 |
| #define simde_vabd_u8 vabd_u8 |
| #define simde_vabdd_f64 vabdd_f64 |
| #define simde_vabdl_high_s16 vabdl_high_s16 |
| #define simde_vabdl_high_s32 vabdl_high_s32 |
| #define simde_vabdl_high_s8 vabdl_high_s8 |
| #define simde_vabdl_high_u16 vabdl_high_u16 |
| #define simde_vabdl_high_u32 vabdl_high_u32 |
| #define simde_vabdl_high_u8 vabdl_high_u8 |
| #define simde_vabdl_s16 vabdl_s16 |
| #define simde_vabdl_s32 vabdl_s32 |
| #define simde_vabdl_s8 vabdl_s8 |
| #define simde_vabdl_u16 vabdl_u16 |
| #define simde_vabdl_u32 vabdl_u32 |
| #define simde_vabdl_u8 vabdl_u8 |
| #define simde_vabdq_f16 vabdq_f16 |
| #define simde_vabdq_f32 vabdq_f32 |
| #define simde_vabdq_f64 vabdq_f64 |
| #define simde_vabdq_s16 vabdq_s16 |
| #define simde_vabdq_s32 vabdq_s32 |
| #define simde_vabdq_s8 vabdq_s8 |
| #define simde_vabdq_u16 vabdq_u16 |
| #define simde_vabdq_u32 vabdq_u32 |
| #define simde_vabdq_u8 vabdq_u8 |
| #define simde_vabds_f32 vabds_f32 |
| #define simde_vabs_f16 vabs_f16 |
| #define simde_vabs_f32 vabs_f32 |
| #define simde_vabs_f64 vabs_f64 |
| #define simde_vabs_s16 vabs_s16 |
| #define simde_vabs_s32 vabs_s32 |
| #define simde_vabs_s64 vabs_s64 |
| #define simde_vabs_s8 vabs_s8 |
| #define simde_vabsd_s64 vabsd_s64 |
| #define simde_vabsq_f16 vabsq_f16 |
| #define simde_vabsq_f32 vabsq_f32 |
| #define simde_vabsq_f64 vabsq_f64 |
| #define simde_vabsq_s16 vabsq_s16 |
| #define simde_vabsq_s32 vabsq_s32 |
| #define simde_vabsq_s64 vabsq_s64 |
| #define simde_vabsq_s8 vabsq_s8 |
| #define simde_vadd_f16 vadd_f16 |
| #define simde_vadd_f32 vadd_f32 |
| #define simde_vadd_f64 vadd_f64 |
| #define simde_vadd_p16 vadd_p16 |
| #define simde_vadd_p64 vadd_p64 |
| #define simde_vadd_p8 vadd_p8 |
| #define simde_vadd_s16 vadd_s16 |
| #define simde_vadd_s32 vadd_s32 |
| #define simde_vadd_s64 vadd_s64 |
| #define simde_vadd_s8 vadd_s8 |
| #define simde_vadd_u16 vadd_u16 |
| #define simde_vadd_u32 vadd_u32 |
| #define simde_vadd_u64 vadd_u64 |
| #define simde_vadd_u8 vadd_u8 |
| #define simde_vaddd_s64 vaddd_s64 |
| #define simde_vaddd_u64 vaddd_u64 |
| #define simde_vaddhn_high_s16 vaddhn_high_s16 |
| #define simde_vaddhn_high_s32 vaddhn_high_s32 |
| #define simde_vaddhn_high_s64 vaddhn_high_s64 |
| #define simde_vaddhn_high_u16 vaddhn_high_u16 |
| #define simde_vaddhn_high_u32 vaddhn_high_u32 |
| #define simde_vaddhn_high_u64 vaddhn_high_u64 |
| #define simde_vaddhn_s16 vaddhn_s16 |
| #define simde_vaddhn_s32 vaddhn_s32 |
| #define simde_vaddhn_s64 vaddhn_s64 |
| #define simde_vaddhn_u16 vaddhn_u16 |
| #define simde_vaddhn_u32 vaddhn_u32 |
| #define simde_vaddhn_u64 vaddhn_u64 |
| #define simde_vaddl_high_s16 vaddl_high_s16 |
| #define simde_vaddl_high_s32 vaddl_high_s32 |
| #define simde_vaddl_high_s8 vaddl_high_s8 |
| #define simde_vaddl_high_u16 vaddl_high_u16 |
| #define simde_vaddl_high_u32 vaddl_high_u32 |
| #define simde_vaddl_high_u8 vaddl_high_u8 |
| #define simde_vaddl_s16 vaddl_s16 |
| #define simde_vaddl_s32 vaddl_s32 |
| #define simde_vaddl_s8 vaddl_s8 |
| #define simde_vaddl_u16 vaddl_u16 |
| #define simde_vaddl_u32 vaddl_u32 |
| #define simde_vaddl_u8 vaddl_u8 |
| #define simde_vaddlv_s16 vaddlv_s16 |
| #define simde_vaddlv_s32 vaddlv_s32 |
| #define simde_vaddlv_s8 vaddlv_s8 |
| #define simde_vaddlv_u16 vaddlv_u16 |
| #define simde_vaddlv_u32 vaddlv_u32 |
| #define simde_vaddlv_u8 vaddlv_u8 |
| #define simde_vaddlvq_s16 vaddlvq_s16 |
| #define simde_vaddlvq_s32 vaddlvq_s32 |
| #define simde_vaddlvq_s8 vaddlvq_s8 |
| #define simde_vaddlvq_u16 vaddlvq_u16 |
| #define simde_vaddlvq_u32 vaddlvq_u32 |
| #define simde_vaddlvq_u8 vaddlvq_u8 |
| #define simde_vaddq_f16 vaddq_f16 |
| #define simde_vaddq_f32 vaddq_f32 |
| #define simde_vaddq_f64 vaddq_f64 |
| #define simde_vaddq_p128 vaddq_p128 |
| #define simde_vaddq_p16 vaddq_p16 |
| #define simde_vaddq_p64 vaddq_p64 |
| #define simde_vaddq_p8 vaddq_p8 |
| #define simde_vaddq_s16 vaddq_s16 |
| #define simde_vaddq_s32 vaddq_s32 |
| #define simde_vaddq_s64 vaddq_s64 |
| #define simde_vaddq_s8 vaddq_s8 |
| #define simde_vaddq_u16 vaddq_u16 |
| #define simde_vaddq_u32 vaddq_u32 |
| #define simde_vaddq_u64 vaddq_u64 |
| #define simde_vaddq_u8 vaddq_u8 |
| #define simde_vaddv_f32 vaddv_f32 |
| #define simde_vaddv_s16 vaddv_s16 |
| #define simde_vaddv_s32 vaddv_s32 |
| #define simde_vaddv_s8 vaddv_s8 |
| #define simde_vaddv_u16 vaddv_u16 |
| #define simde_vaddv_u32 vaddv_u32 |
| #define simde_vaddv_u8 vaddv_u8 |
| #define simde_vaddvq_f32 vaddvq_f32 |
| #define simde_vaddvq_f64 vaddvq_f64 |
| #define simde_vaddvq_s16 vaddvq_s16 |
| #define simde_vaddvq_s32 vaddvq_s32 |
| #define simde_vaddvq_s64 vaddvq_s64 |
| #define simde_vaddvq_s8 vaddvq_s8 |
| #define simde_vaddvq_u16 vaddvq_u16 |
| #define simde_vaddvq_u32 vaddvq_u32 |
| #define simde_vaddvq_u64 vaddvq_u64 |
| #define simde_vaddvq_u8 vaddvq_u8 |
| #define simde_vaddw_high_s16 vaddw_high_s16 |
| #define simde_vaddw_high_s32 vaddw_high_s32 |
| #define simde_vaddw_high_s8 vaddw_high_s8 |
| #define simde_vaddw_high_u16 vaddw_high_u16 |
| #define simde_vaddw_high_u32 vaddw_high_u32 |
| #define simde_vaddw_high_u8 vaddw_high_u8 |
| #define simde_vaddw_s16 vaddw_s16 |
| #define simde_vaddw_s32 vaddw_s32 |
| #define simde_vaddw_s8 vaddw_s8 |
| #define simde_vaddw_u16 vaddw_u16 |
| #define simde_vaddw_u32 vaddw_u32 |
| #define simde_vaddw_u8 vaddw_u8 |
| #define simde_vaesdq_u8 vaesdq_u8 |
| #define simde_vaeseq_u8 vaeseq_u8 |
| #define simde_vaesimcq_u8 vaesimcq_u8 |
| #define simde_vaesmcq_u8 vaesmcq_u8 |
| #define simde_vand_s16 vand_s16 |
| #define simde_vand_s32 vand_s32 |
| #define simde_vand_s64 vand_s64 |
| #define simde_vand_s8 vand_s8 |
| #define simde_vand_u16 vand_u16 |
| #define simde_vand_u32 vand_u32 |
| #define simde_vand_u64 vand_u64 |
| #define simde_vand_u8 vand_u8 |
| #define simde_vandq_s16 vandq_s16 |
| #define simde_vandq_s32 vandq_s32 |
| #define simde_vandq_s64 vandq_s64 |
| #define simde_vandq_s8 vandq_s8 |
| #define simde_vandq_u16 vandq_u16 |
| #define simde_vandq_u32 vandq_u32 |
| #define simde_vandq_u64 vandq_u64 |
| #define simde_vandq_u8 vandq_u8 |
| #define simde_vbcaxq_s16 vbcaxq_s16 |
| #define simde_vbcaxq_s32 vbcaxq_s32 |
| #define simde_vbcaxq_s64 vbcaxq_s64 |
| #define simde_vbcaxq_s8 vbcaxq_s8 |
| #define simde_vbcaxq_u16 vbcaxq_u16 |
| #define simde_vbcaxq_u32 vbcaxq_u32 |
| #define simde_vbcaxq_u64 vbcaxq_u64 |
| #define simde_vbcaxq_u8 vbcaxq_u8 |
| #define simde_vbfdot_f32 vbfdot_f32 |
| #define simde_vbfdot_lane_f32 vbfdot_lane_f32 |
| #define simde_vbfdot_laneq_f32 vbfdot_laneq_f32 |
| #define simde_vbfdotq_f32 vbfdotq_f32 |
| #define simde_vbfdotq_lane_f32 vbfdotq_lane_f32 |
| #define simde_vbfdotq_laneq_f32 vbfdotq_laneq_f32 |
| #define simde_vbfmlalbq_f32 vbfmlalbq_f32 |
| #define simde_vbfmlalbq_lane_f32 vbfmlalbq_lane_f32 |
| #define simde_vbfmlalbq_laneq_f32 vbfmlalbq_laneq_f32 |
| #define simde_vbfmlaltq_f32 vbfmlaltq_f32 |
| #define simde_vbfmlaltq_lane_f32 vbfmlaltq_lane_f32 |
| #define simde_vbfmlaltq_laneq_f32 vbfmlaltq_laneq_f32 |
| #define simde_vbfmmlaq_f32 vbfmmlaq_f32 |
| #define simde_vbic_s16 vbic_s16 |
| #define simde_vbic_s32 vbic_s32 |
| #define simde_vbic_s64 vbic_s64 |
| #define simde_vbic_s8 vbic_s8 |
| #define simde_vbic_u16 vbic_u16 |
| #define simde_vbic_u32 vbic_u32 |
| #define simde_vbic_u64 vbic_u64 |
| #define simde_vbic_u8 vbic_u8 |
| #define simde_vbicq_s16 vbicq_s16 |
| #define simde_vbicq_s32 vbicq_s32 |
| #define simde_vbicq_s64 vbicq_s64 |
| #define simde_vbicq_s8 vbicq_s8 |
| #define simde_vbicq_u16 vbicq_u16 |
| #define simde_vbicq_u32 vbicq_u32 |
| #define simde_vbicq_u64 vbicq_u64 |
| #define simde_vbicq_u8 vbicq_u8 |
| #define simde_vbsl_f16 vbsl_f16 |
| #define simde_vbsl_f32 vbsl_f32 |
| #define simde_vbsl_f64 vbsl_f64 |
| #define simde_vbsl_p16 vbsl_p16 |
| #define simde_vbsl_p64 vbsl_p64 |
| #define simde_vbsl_p8 vbsl_p8 |
| #define simde_vbsl_s16 vbsl_s16 |
| #define simde_vbsl_s32 vbsl_s32 |
| #define simde_vbsl_s64 vbsl_s64 |
| #define simde_vbsl_s8 vbsl_s8 |
| #define simde_vbsl_u16 vbsl_u16 |
| #define simde_vbsl_u32 vbsl_u32 |
| #define simde_vbsl_u64 vbsl_u64 |
| #define simde_vbsl_u8 vbsl_u8 |
| #define simde_vbslq_f16 vbslq_f16 |
| #define simde_vbslq_f32 vbslq_f32 |
| #define simde_vbslq_f64 vbslq_f64 |
| #define simde_vbslq_p16 vbslq_p16 |
| #define simde_vbslq_p64 vbslq_p64 |
| #define simde_vbslq_p8 vbslq_p8 |
| #define simde_vbslq_s16 vbslq_s16 |
| #define simde_vbslq_s32 vbslq_s32 |
| #define simde_vbslq_s64 vbslq_s64 |
| #define simde_vbslq_s8 vbslq_s8 |
| #define simde_vbslq_u16 vbslq_u16 |
| #define simde_vbslq_u32 vbslq_u32 |
| #define simde_vbslq_u64 vbslq_u64 |
| #define simde_vbslq_u8 vbslq_u8 |
| #define simde_vcadd_rot270_f16 vcadd_rot270_f16 |
| #define simde_vcadd_rot270_f32 vcadd_rot270_f32 |
| #define simde_vcadd_rot90_f16 vcadd_rot90_f16 |
| #define simde_vcadd_rot90_f32 vcadd_rot90_f32 |
| #define simde_vcaddq_rot270_f16 vcaddq_rot270_f16 |
| #define simde_vcaddq_rot270_f32 vcaddq_rot270_f32 |
| #define simde_vcaddq_rot270_f64 vcaddq_rot270_f64 |
| #define simde_vcaddq_rot90_f16 vcaddq_rot90_f16 |
| #define simde_vcaddq_rot90_f32 vcaddq_rot90_f32 |
| #define simde_vcaddq_rot90_f64 vcaddq_rot90_f64 |
| #define simde_vcage_f16 vcage_f16 |
| #define simde_vcage_f32 vcage_f32 |
| #define simde_vcage_f64 vcage_f64 |
| #define simde_vcaged_f64 vcaged_f64 |
| #define simde_vcageq_f16 vcageq_f16 |
| #define simde_vcageq_f32 vcageq_f32 |
| #define simde_vcageq_f64 vcageq_f64 |
| #define simde_vcages_f32 vcages_f32 |
| #define simde_vcagt_f16 vcagt_f16 |
| #define simde_vcagt_f32 vcagt_f32 |
| #define simde_vcagt_f64 vcagt_f64 |
| #define simde_vcagtd_f64 vcagtd_f64 |
| #define simde_vcagtq_f16 vcagtq_f16 |
| #define simde_vcagtq_f32 vcagtq_f32 |
| #define simde_vcagtq_f64 vcagtq_f64 |
| #define simde_vcagts_f32 vcagts_f32 |
| #define simde_vcale_f16 vcale_f16 |
| #define simde_vcale_f32 vcale_f32 |
| #define simde_vcale_f64 vcale_f64 |
| #define simde_vcaled_f64 vcaled_f64 |
| #define simde_vcaleq_f16 vcaleq_f16 |
| #define simde_vcaleq_f32 vcaleq_f32 |
| #define simde_vcaleq_f64 vcaleq_f64 |
| #define simde_vcales_f32 vcales_f32 |
| #define simde_vcalt_f16 vcalt_f16 |
| #define simde_vcalt_f32 vcalt_f32 |
| #define simde_vcalt_f64 vcalt_f64 |
| #define simde_vcaltd_f64 vcaltd_f64 |
| #define simde_vcaltq_f16 vcaltq_f16 |
| #define simde_vcaltq_f32 vcaltq_f32 |
| #define simde_vcaltq_f64 vcaltq_f64 |
| #define simde_vcalts_f32 vcalts_f32 |
| #define simde_vceq_f16 vceq_f16 |
| #define simde_vceq_f32 vceq_f32 |
| #define simde_vceq_f64 vceq_f64 |
| #define simde_vceq_p64 vceq_p64 |
| #define simde_vceq_p8 vceq_p8 |
| #define simde_vceq_s16 vceq_s16 |
| #define simde_vceq_s32 vceq_s32 |
| #define simde_vceq_s64 vceq_s64 |
| #define simde_vceq_s8 vceq_s8 |
| #define simde_vceq_u16 vceq_u16 |
| #define simde_vceq_u32 vceq_u32 |
| #define simde_vceq_u64 vceq_u64 |
| #define simde_vceq_u8 vceq_u8 |
| #define simde_vceqd_f64 vceqd_f64 |
| #define simde_vceqd_s64 vceqd_s64 |
| #define simde_vceqd_u64 vceqd_u64 |
| #define simde_vceqq_f16 vceqq_f16 |
| #define simde_vceqq_f32 vceqq_f32 |
| #define simde_vceqq_f64 vceqq_f64 |
| #define simde_vceqq_p64 vceqq_p64 |
| #define simde_vceqq_p8 vceqq_p8 |
| #define simde_vceqq_s16 vceqq_s16 |
| #define simde_vceqq_s32 vceqq_s32 |
| #define simde_vceqq_s64 vceqq_s64 |
| #define simde_vceqq_s8 vceqq_s8 |
| #define simde_vceqq_u16 vceqq_u16 |
| #define simde_vceqq_u32 vceqq_u32 |
| #define simde_vceqq_u64 vceqq_u64 |
| #define simde_vceqq_u8 vceqq_u8 |
| #define simde_vceqs_f32 vceqs_f32 |
| #define simde_vceqz_f16 vceqz_f16 |
| #define simde_vceqz_f32 vceqz_f32 |
| #define simde_vceqz_f64 vceqz_f64 |
| #define simde_vceqz_p64 vceqz_p64 |
| #define simde_vceqz_p8 vceqz_p8 |
| #define simde_vceqz_s16 vceqz_s16 |
| #define simde_vceqz_s32 vceqz_s32 |
| #define simde_vceqz_s64 vceqz_s64 |
| #define simde_vceqz_s8 vceqz_s8 |
| #define simde_vceqz_u16 vceqz_u16 |
| #define simde_vceqz_u32 vceqz_u32 |
| #define simde_vceqz_u64 vceqz_u64 |
| #define simde_vceqz_u8 vceqz_u8 |
| #define simde_vceqzd_f64 vceqzd_f64 |
| #define simde_vceqzd_s64 vceqzd_s64 |
| #define simde_vceqzd_u64 vceqzd_u64 |
| #define simde_vceqzq_f16 vceqzq_f16 |
| #define simde_vceqzq_f32 vceqzq_f32 |
| #define simde_vceqzq_f64 vceqzq_f64 |
| #define simde_vceqzq_p64 vceqzq_p64 |
| #define simde_vceqzq_p8 vceqzq_p8 |
| #define simde_vceqzq_s16 vceqzq_s16 |
| #define simde_vceqzq_s32 vceqzq_s32 |
| #define simde_vceqzq_s64 vceqzq_s64 |
| #define simde_vceqzq_s8 vceqzq_s8 |
| #define simde_vceqzq_u16 vceqzq_u16 |
| #define simde_vceqzq_u32 vceqzq_u32 |
| #define simde_vceqzq_u64 vceqzq_u64 |
| #define simde_vceqzq_u8 vceqzq_u8 |
| #define simde_vceqzs_f32 vceqzs_f32 |
| #define simde_vcge_f16 vcge_f16 |
| #define simde_vcge_f32 vcge_f32 |
| #define simde_vcge_f64 vcge_f64 |
| #define simde_vcge_s16 vcge_s16 |
| #define simde_vcge_s32 vcge_s32 |
| #define simde_vcge_s64 vcge_s64 |
| #define simde_vcge_s8 vcge_s8 |
| #define simde_vcge_u16 vcge_u16 |
| #define simde_vcge_u32 vcge_u32 |
| #define simde_vcge_u64 vcge_u64 |
| #define simde_vcge_u8 vcge_u8 |
| #define simde_vcged_f64 vcged_f64 |
| #define simde_vcged_s64 vcged_s64 |
| #define simde_vcged_u64 vcged_u64 |
| #define simde_vcgeq_f16 vcgeq_f16 |
| #define simde_vcgeq_f32 vcgeq_f32 |
| #define simde_vcgeq_f64 vcgeq_f64 |
| #define simde_vcgeq_s16 vcgeq_s16 |
| #define simde_vcgeq_s32 vcgeq_s32 |
| #define simde_vcgeq_s64 vcgeq_s64 |
| #define simde_vcgeq_s8 vcgeq_s8 |
| #define simde_vcgeq_u16 vcgeq_u16 |
| #define simde_vcgeq_u32 vcgeq_u32 |
| #define simde_vcgeq_u64 vcgeq_u64 |
| #define simde_vcgeq_u8 vcgeq_u8 |
| #define simde_vcges_f32 vcges_f32 |
| #define simde_vcgez_f16 vcgez_f16 |
| #define simde_vcgez_f32 vcgez_f32 |
| #define simde_vcgez_f64 vcgez_f64 |
| #define simde_vcgez_s16 vcgez_s16 |
| #define simde_vcgez_s32 vcgez_s32 |
| #define simde_vcgez_s64 vcgez_s64 |
| #define simde_vcgez_s8 vcgez_s8 |
| #define simde_vcgezd_f64 vcgezd_f64 |
| #define simde_vcgezd_s64 vcgezd_s64 |
| #define simde_vcgezq_f16 vcgezq_f16 |
| #define simde_vcgezq_f32 vcgezq_f32 |
| #define simde_vcgezq_f64 vcgezq_f64 |
| #define simde_vcgezq_s16 vcgezq_s16 |
| #define simde_vcgezq_s32 vcgezq_s32 |
| #define simde_vcgezq_s64 vcgezq_s64 |
| #define simde_vcgezq_s8 vcgezq_s8 |
| #define simde_vcgezs_f32 vcgezs_f32 |
| #define simde_vcgt_f16 vcgt_f16 |
| #define simde_vcgt_f32 vcgt_f32 |
| #define simde_vcgt_f64 vcgt_f64 |
| #define simde_vcgt_s16 vcgt_s16 |
| #define simde_vcgt_s32 vcgt_s32 |
| #define simde_vcgt_s64 vcgt_s64 |
| #define simde_vcgt_s8 vcgt_s8 |
| #define simde_vcgt_u16 vcgt_u16 |
| #define simde_vcgt_u32 vcgt_u32 |
| #define simde_vcgt_u64 vcgt_u64 |
| #define simde_vcgt_u8 vcgt_u8 |
| #define simde_vcgtd_f64 vcgtd_f64 |
| #define simde_vcgtd_s64 vcgtd_s64 |
| #define simde_vcgtd_u64 vcgtd_u64 |
| #define simde_vcgtq_f16 vcgtq_f16 |
| #define simde_vcgtq_f32 vcgtq_f32 |
| #define simde_vcgtq_f64 vcgtq_f64 |
| #define simde_vcgtq_s16 vcgtq_s16 |
| #define simde_vcgtq_s32 vcgtq_s32 |
| #define simde_vcgtq_s64 vcgtq_s64 |
| #define simde_vcgtq_s8 vcgtq_s8 |
| #define simde_vcgtq_u16 vcgtq_u16 |
| #define simde_vcgtq_u32 vcgtq_u32 |
| #define simde_vcgtq_u64 vcgtq_u64 |
| #define simde_vcgtq_u8 vcgtq_u8 |
| #define simde_vcgts_f32 vcgts_f32 |
| #define simde_vcgtz_f16 vcgtz_f16 |
| #define simde_vcgtz_f32 vcgtz_f32 |
| #define simde_vcgtz_f64 vcgtz_f64 |
| #define simde_vcgtz_s16 vcgtz_s16 |
| #define simde_vcgtz_s32 vcgtz_s32 |
| #define simde_vcgtz_s64 vcgtz_s64 |
| #define simde_vcgtz_s8 vcgtz_s8 |
| #define simde_vcgtzd_f64 vcgtzd_f64 |
| #define simde_vcgtzd_s64 vcgtzd_s64 |
| #define simde_vcgtzq_f16 vcgtzq_f16 |
| #define simde_vcgtzq_f32 vcgtzq_f32 |
| #define simde_vcgtzq_f64 vcgtzq_f64 |
| #define simde_vcgtzq_s16 vcgtzq_s16 |
| #define simde_vcgtzq_s32 vcgtzq_s32 |
| #define simde_vcgtzq_s64 vcgtzq_s64 |
| #define simde_vcgtzq_s8 vcgtzq_s8 |
| #define simde_vcgtzs_f32 vcgtzs_f32 |
| #define simde_vcle_f16 vcle_f16 |
| #define simde_vcle_f32 vcle_f32 |
| #define simde_vcle_f64 vcle_f64 |
| #define simde_vcle_s16 vcle_s16 |
| #define simde_vcle_s32 vcle_s32 |
| #define simde_vcle_s64 vcle_s64 |
| #define simde_vcle_s8 vcle_s8 |
| #define simde_vcle_u16 vcle_u16 |
| #define simde_vcle_u32 vcle_u32 |
| #define simde_vcle_u64 vcle_u64 |
| #define simde_vcle_u8 vcle_u8 |
| #define simde_vcled_f64 vcled_f64 |
| #define simde_vcled_s64 vcled_s64 |
| #define simde_vcled_u64 vcled_u64 |
| #define simde_vcleq_f16 vcleq_f16 |
| #define simde_vcleq_f32 vcleq_f32 |
| #define simde_vcleq_f64 vcleq_f64 |
| #define simde_vcleq_s16 vcleq_s16 |
| #define simde_vcleq_s32 vcleq_s32 |
| #define simde_vcleq_s64 vcleq_s64 |
| #define simde_vcleq_s8 vcleq_s8 |
| #define simde_vcleq_u16 vcleq_u16 |
| #define simde_vcleq_u32 vcleq_u32 |
| #define simde_vcleq_u64 vcleq_u64 |
| #define simde_vcleq_u8 vcleq_u8 |
| #define simde_vcles_f32 vcles_f32 |
| #define simde_vclez_f16 vclez_f16 |
| #define simde_vclez_f32 vclez_f32 |
| #define simde_vclez_f64 vclez_f64 |
| #define simde_vclez_s16 vclez_s16 |
| #define simde_vclez_s32 vclez_s32 |
| #define simde_vclez_s64 vclez_s64 |
| #define simde_vclez_s8 vclez_s8 |
| #define simde_vclezd_f64 vclezd_f64 |
| #define simde_vclezd_s64 vclezd_s64 |
| #define simde_vclezq_f16 vclezq_f16 |
| #define simde_vclezq_f32 vclezq_f32 |
| #define simde_vclezq_f64 vclezq_f64 |
| #define simde_vclezq_s16 vclezq_s16 |
| #define simde_vclezq_s32 vclezq_s32 |
| #define simde_vclezq_s64 vclezq_s64 |
| #define simde_vclezq_s8 vclezq_s8 |
| #define simde_vclezs_f32 vclezs_f32 |
| #define simde_vcls_s16 vcls_s16 |
| #define simde_vcls_s32 vcls_s32 |
| #define simde_vcls_s8 vcls_s8 |
| #define simde_vcls_u16 vcls_u16 |
| #define simde_vcls_u32 vcls_u32 |
| #define simde_vcls_u8 vcls_u8 |
| #define simde_vclsq_s16 vclsq_s16 |
| #define simde_vclsq_s32 vclsq_s32 |
| #define simde_vclsq_s8 vclsq_s8 |
| #define simde_vclsq_u16 vclsq_u16 |
| #define simde_vclsq_u32 vclsq_u32 |
| #define simde_vclsq_u8 vclsq_u8 |
| #define simde_vclt_f16 vclt_f16 |
| #define simde_vclt_f32 vclt_f32 |
| #define simde_vclt_f64 vclt_f64 |
| #define simde_vclt_s16 vclt_s16 |
| #define simde_vclt_s32 vclt_s32 |
| #define simde_vclt_s64 vclt_s64 |
| #define simde_vclt_s8 vclt_s8 |
| #define simde_vclt_u16 vclt_u16 |
| #define simde_vclt_u32 vclt_u32 |
| #define simde_vclt_u64 vclt_u64 |
| #define simde_vclt_u8 vclt_u8 |
| #define simde_vcltd_f64 vcltd_f64 |
| #define simde_vcltd_s64 vcltd_s64 |
| #define simde_vcltd_u64 vcltd_u64 |
| #define simde_vcltq_f16 vcltq_f16 |
| #define simde_vcltq_f32 vcltq_f32 |
| #define simde_vcltq_f64 vcltq_f64 |
| #define simde_vcltq_s16 vcltq_s16 |
| #define simde_vcltq_s32 vcltq_s32 |
| #define simde_vcltq_s64 vcltq_s64 |
| #define simde_vcltq_s8 vcltq_s8 |
| #define simde_vcltq_u16 vcltq_u16 |
| #define simde_vcltq_u32 vcltq_u32 |
| #define simde_vcltq_u64 vcltq_u64 |
| #define simde_vcltq_u8 vcltq_u8 |
| #define simde_vclts_f32 vclts_f32 |
| #define simde_vcltz_f16 vcltz_f16 |
| #define simde_vcltz_f32 vcltz_f32 |
| #define simde_vcltz_f64 vcltz_f64 |
| #define simde_vcltz_s16 vcltz_s16 |
| #define simde_vcltz_s32 vcltz_s32 |
| #define simde_vcltz_s64 vcltz_s64 |
| #define simde_vcltz_s8 vcltz_s8 |
| #define simde_vcltzd_f64 vcltzd_f64 |
| #define simde_vcltzd_s64 vcltzd_s64 |
| #define simde_vcltzq_f16 vcltzq_f16 |
| #define simde_vcltzq_f32 vcltzq_f32 |
| #define simde_vcltzq_f64 vcltzq_f64 |
| #define simde_vcltzq_s16 vcltzq_s16 |
| #define simde_vcltzq_s32 vcltzq_s32 |
| #define simde_vcltzq_s64 vcltzq_s64 |
| #define simde_vcltzq_s8 vcltzq_s8 |
| #define simde_vcltzs_f32 vcltzs_f32 |
| #define simde_vclz_s16 vclz_s16 |
| #define simde_vclz_s32 vclz_s32 |
| #define simde_vclz_s8 vclz_s8 |
| #define simde_vclz_u16 vclz_u16 |
| #define simde_vclz_u32 vclz_u32 |
| #define simde_vclz_u8 vclz_u8 |
| #define simde_vclzq_s16 vclzq_s16 |
| #define simde_vclzq_s32 vclzq_s32 |
| #define simde_vclzq_s8 vclzq_s8 |
| #define simde_vclzq_u16 vclzq_u16 |
| #define simde_vclzq_u32 vclzq_u32 |
| #define simde_vclzq_u8 vclzq_u8 |
| #define simde_vcmla_f16 vcmla_f16 |
| #define simde_vcmla_f32 vcmla_f32 |
| #define simde_vcmla_lane_f16 vcmla_lane_f16 |
| #define simde_vcmla_lane_f32 vcmla_lane_f32 |
| #define simde_vcmla_laneq_f16 vcmla_laneq_f16 |
| #define simde_vcmla_laneq_f32 vcmla_laneq_f32 |
| #define simde_vcmla_rot180_f16 vcmla_rot180_f16 |
| #define simde_vcmla_rot180_f32 vcmla_rot180_f32 |
| #define simde_vcmla_rot180_lane_f16 vcmla_rot180_lane_f16 |
| #define simde_vcmla_rot180_lane_f32 vcmla_rot180_lane_f32 |
| #define simde_vcmla_rot180_laneq_f16 vcmla_rot180_laneq_f16 |
| #define simde_vcmla_rot180_laneq_f32 vcmla_rot180_laneq_f32 |
| #define simde_vcmla_rot270_f16 vcmla_rot270_f16 |
| #define simde_vcmla_rot270_f32 vcmla_rot270_f32 |
| #define simde_vcmla_rot270_lane_f16 vcmla_rot270_lane_f16 |
| #define simde_vcmla_rot270_lane_f32 vcmla_rot270_lane_f32 |
| #define simde_vcmla_rot270_laneq_f16 vcmla_rot270_laneq_f16 |
| #define simde_vcmla_rot270_laneq_f32 vcmla_rot270_laneq_f32 |
| #define simde_vcmla_rot90_f16 vcmla_rot90_f16 |
| #define simde_vcmla_rot90_f32 vcmla_rot90_f32 |
| #define simde_vcmla_rot90_lane_f16 vcmla_rot90_lane_f16 |
| #define simde_vcmla_rot90_lane_f32 vcmla_rot90_lane_f32 |
| #define simde_vcmla_rot90_laneq_f16 vcmla_rot90_laneq_f16 |
| #define simde_vcmla_rot90_laneq_f32 vcmla_rot90_laneq_f32 |
| #define simde_vcmlaq_f16 vcmlaq_f16 |
| #define simde_vcmlaq_f32 vcmlaq_f32 |
| #define simde_vcmlaq_f64 vcmlaq_f64 |
| #define simde_vcmlaq_lane_f16 vcmlaq_lane_f16 |
| #define simde_vcmlaq_lane_f32 vcmlaq_lane_f32 |
| #define simde_vcmlaq_laneq_f16 vcmlaq_laneq_f16 |
| #define simde_vcmlaq_laneq_f32 vcmlaq_laneq_f32 |
| #define simde_vcmlaq_rot180_f16 vcmlaq_rot180_f16 |
| #define simde_vcmlaq_rot180_f32 vcmlaq_rot180_f32 |
| #define simde_vcmlaq_rot180_f64 vcmlaq_rot180_f64 |
| #define simde_vcmlaq_rot180_lane_f16 vcmlaq_rot180_lane_f16 |
| #define simde_vcmlaq_rot180_lane_f32 vcmlaq_rot180_lane_f32 |
| #define simde_vcmlaq_rot180_laneq_f16 vcmlaq_rot180_laneq_f16 |
| #define simde_vcmlaq_rot180_laneq_f32 vcmlaq_rot180_laneq_f32 |
| #define simde_vcmlaq_rot270_f16 vcmlaq_rot270_f16 |
| #define simde_vcmlaq_rot270_f32 vcmlaq_rot270_f32 |
| #define simde_vcmlaq_rot270_f64 vcmlaq_rot270_f64 |
| #define simde_vcmlaq_rot270_lane_f16 vcmlaq_rot270_lane_f16 |
| #define simde_vcmlaq_rot270_lane_f32 vcmlaq_rot270_lane_f32 |
| #define simde_vcmlaq_rot270_laneq_f16 vcmlaq_rot270_laneq_f16 |
| #define simde_vcmlaq_rot270_laneq_f32 vcmlaq_rot270_laneq_f32 |
| #define simde_vcmlaq_rot90_f16 vcmlaq_rot90_f16 |
| #define simde_vcmlaq_rot90_f32 vcmlaq_rot90_f32 |
| #define simde_vcmlaq_rot90_f64 vcmlaq_rot90_f64 |
| #define simde_vcmlaq_rot90_lane_f16 vcmlaq_rot90_lane_f16 |
| #define simde_vcmlaq_rot90_lane_f32 vcmlaq_rot90_lane_f32 |
| #define simde_vcmlaq_rot90_laneq_f16 vcmlaq_rot90_laneq_f16 |
| #define simde_vcmlaq_rot90_laneq_f32 vcmlaq_rot90_laneq_f32 |
| #define simde_vcnt_p8 vcnt_p8 |
| #define simde_vcnt_s8 vcnt_s8 |
| #define simde_vcnt_u8 vcnt_u8 |
| #define simde_vcntq_p8 vcntq_p8 |
| #define simde_vcntq_s8 vcntq_s8 |
| #define simde_vcntq_u8 vcntq_u8 |
| #define simde_vcombine_bf16 vcombine_bf16 |
| #define simde_vcombine_f16 vcombine_f16 |
| #define simde_vcombine_f32 vcombine_f32 |
| #define simde_vcombine_f64 vcombine_f64 |
| #define simde_vcombine_p16 vcombine_p16 |
| #define simde_vcombine_p64 vcombine_p64 |
| #define simde_vcombine_p8 vcombine_p8 |
| #define simde_vcombine_s16 vcombine_s16 |
| #define simde_vcombine_s32 vcombine_s32 |
| #define simde_vcombine_s64 vcombine_s64 |
| #define simde_vcombine_s8 vcombine_s8 |
| #define simde_vcombine_u16 vcombine_u16 |
| #define simde_vcombine_u32 vcombine_u32 |
| #define simde_vcombine_u64 vcombine_u64 |
| #define simde_vcombine_u8 vcombine_u8 |
| #define simde_vcopy_lane_bf16 vcopy_lane_bf16 |
| #define simde_vcopy_lane_f32 vcopy_lane_f32 |
| #define simde_vcopy_lane_f64 vcopy_lane_f64 |
| #define simde_vcopy_lane_p16 vcopy_lane_p16 |
| #define simde_vcopy_lane_p64 vcopy_lane_p64 |
| #define simde_vcopy_lane_p8 vcopy_lane_p8 |
| #define simde_vcopy_lane_s16 vcopy_lane_s16 |
| #define simde_vcopy_lane_s32 vcopy_lane_s32 |
| #define simde_vcopy_lane_s64 vcopy_lane_s64 |
| #define simde_vcopy_lane_s8 vcopy_lane_s8 |
| #define simde_vcopy_lane_u16 vcopy_lane_u16 |
| #define simde_vcopy_lane_u32 vcopy_lane_u32 |
| #define simde_vcopy_lane_u64 vcopy_lane_u64 |
| #define simde_vcopy_lane_u8 vcopy_lane_u8 |
| #define simde_vcopy_laneq_bf16 vcopy_laneq_bf16 |
| #define simde_vcopy_laneq_f32 vcopy_laneq_f32 |
| #define simde_vcopy_laneq_f64 vcopy_laneq_f64 |
| #define simde_vcopy_laneq_p16 vcopy_laneq_p16 |
| #define simde_vcopy_laneq_p64 vcopy_laneq_p64 |
| #define simde_vcopy_laneq_p8 vcopy_laneq_p8 |
| #define simde_vcopy_laneq_s16 vcopy_laneq_s16 |
| #define simde_vcopy_laneq_s32 vcopy_laneq_s32 |
| #define simde_vcopy_laneq_s64 vcopy_laneq_s64 |
| #define simde_vcopy_laneq_s8 vcopy_laneq_s8 |
| #define simde_vcopy_laneq_u16 vcopy_laneq_u16 |
| #define simde_vcopy_laneq_u32 vcopy_laneq_u32 |
| #define simde_vcopy_laneq_u64 vcopy_laneq_u64 |
| #define simde_vcopy_laneq_u8 vcopy_laneq_u8 |
| #define simde_vcopyq_lane_bf16 vcopyq_lane_bf16 |
| #define simde_vcopyq_lane_f32 vcopyq_lane_f32 |
| #define simde_vcopyq_lane_f64 vcopyq_lane_f64 |
| #define simde_vcopyq_lane_p16 vcopyq_lane_p16 |
| #define simde_vcopyq_lane_p64 vcopyq_lane_p64 |
| #define simde_vcopyq_lane_p8 vcopyq_lane_p8 |
| #define simde_vcopyq_lane_s16 vcopyq_lane_s16 |
| #define simde_vcopyq_lane_s32 vcopyq_lane_s32 |
| #define simde_vcopyq_lane_s64 vcopyq_lane_s64 |
| #define simde_vcopyq_lane_s8 vcopyq_lane_s8 |
| #define simde_vcopyq_lane_u16 vcopyq_lane_u16 |
| #define simde_vcopyq_lane_u32 vcopyq_lane_u32 |
| #define simde_vcopyq_lane_u64 vcopyq_lane_u64 |
| #define simde_vcopyq_lane_u8 vcopyq_lane_u8 |
| #define simde_vcopyq_laneq_bf16 vcopyq_laneq_bf16 |
| #define simde_vcopyq_laneq_f32 vcopyq_laneq_f32 |
| #define simde_vcopyq_laneq_f64 vcopyq_laneq_f64 |
| #define simde_vcopyq_laneq_p16 vcopyq_laneq_p16 |
| #define simde_vcopyq_laneq_p64 vcopyq_laneq_p64 |
| #define simde_vcopyq_laneq_p8 vcopyq_laneq_p8 |
| #define simde_vcopyq_laneq_s16 vcopyq_laneq_s16 |
| #define simde_vcopyq_laneq_s32 vcopyq_laneq_s32 |
| #define simde_vcopyq_laneq_s64 vcopyq_laneq_s64 |
| #define simde_vcopyq_laneq_s8 vcopyq_laneq_s8 |
| #define simde_vcopyq_laneq_u16 vcopyq_laneq_u16 |
| #define simde_vcopyq_laneq_u32 vcopyq_laneq_u32 |
| #define simde_vcopyq_laneq_u64 vcopyq_laneq_u64 |
| #define simde_vcopyq_laneq_u8 vcopyq_laneq_u8 |
| #define simde_vcreate_bf16 vcreate_bf16 |
| #define simde_vcreate_f16 vcreate_f16 |
| #define simde_vcreate_f32 vcreate_f32 |
| #define simde_vcreate_f64 vcreate_f64 |
| #define simde_vcreate_p16 vcreate_p16 |
| #define simde_vcreate_p64 vcreate_p64 |
| #define simde_vcreate_p8 vcreate_p8 |
| #define simde_vcreate_s16 vcreate_s16 |
| #define simde_vcreate_s32 vcreate_s32 |
| #define simde_vcreate_s64 vcreate_s64 |
| #define simde_vcreate_s8 vcreate_s8 |
| #define simde_vcreate_u16 vcreate_u16 |
| #define simde_vcreate_u32 vcreate_u32 |
| #define simde_vcreate_u64 vcreate_u64 |
| #define simde_vcreate_u8 vcreate_u8 |
| #define simde_vcvt_bf16_f32 vcvt_bf16_f32 |
| #define simde_vcvt_f16_f32 vcvt_f16_f32 |
| #define simde_vcvt_f16_s16 vcvt_f16_s16 |
| #define simde_vcvt_f16_u16 vcvt_f16_u16 |
| #define simde_vcvt_f32_bf16 vcvt_f32_bf16 |
| #define simde_vcvt_f32_f16 vcvt_f32_f16 |
| #define simde_vcvt_f32_f64 vcvt_f32_f64 |
| #define simde_vcvt_f32_s32 vcvt_f32_s32 |
| #define simde_vcvt_f32_u32 vcvt_f32_u32 |
| #define simde_vcvt_f64_f32 vcvt_f64_f32 |
| #define simde_vcvt_f64_s64 vcvt_f64_s64 |
| #define simde_vcvt_f64_u64 vcvt_f64_u64 |
| #define simde_vcvt_high_f16_f32 vcvt_high_f16_f32 |
| #define simde_vcvt_high_f32_f16 vcvt_high_f32_f16 |
| #define simde_vcvt_high_f32_f64 vcvt_high_f32_f64 |
| #define simde_vcvt_high_f64_f32 vcvt_high_f64_f32 |
| #define simde_vcvt_n_f16_s16 vcvt_n_f16_s16 |
| #define simde_vcvt_n_f16_u16 vcvt_n_f16_u16 |
| #define simde_vcvt_n_f32_s32 vcvt_n_f32_s32 |
| #define simde_vcvt_n_f32_u32 vcvt_n_f32_u32 |
| #define simde_vcvt_n_f64_s64 vcvt_n_f64_s64 |
| #define simde_vcvt_n_f64_u64 vcvt_n_f64_u64 |
| #define simde_vcvt_n_s32_f32 vcvt_n_s32_f32 |
| #define simde_vcvt_n_s64_f64 vcvt_n_s64_f64 |
| #define simde_vcvt_n_u16_f16 vcvt_n_u16_f16 |
| #define simde_vcvt_n_u32_f32 vcvt_n_u32_f32 |
| #define simde_vcvt_n_u64_f64 vcvt_n_u64_f64 |
| #define simde_vcvt_s32_f32 vcvt_s32_f32 |
| #define simde_vcvt_s64_f64 vcvt_s64_f64 |
| #define simde_vcvt_u16_f16 vcvt_u16_f16 |
| #define simde_vcvt_u32_f32 vcvt_u32_f32 |
| #define simde_vcvt_u64_f64 vcvt_u64_f64 |
| #define simde_vcvta_s32_f32 vcvta_s32_f32 |
| #define simde_vcvta_s64_f64 vcvta_s64_f64 |
| #define simde_vcvta_u16_f16 vcvta_u16_f16 |
| #define simde_vcvta_u32_f32 vcvta_u32_f32 |
| #define simde_vcvta_u64_f64 vcvta_u64_f64 |
| #define simde_vcvtad_s64_f64 vcvtad_s64_f64 |
| #define simde_vcvtad_u64_f64 vcvtad_u64_f64 |
| #define simde_vcvtah_f32_bf16 vcvtah_f32_bf16 |
| #define simde_vcvtaq_s32_f32 vcvtaq_s32_f32 |
| #define simde_vcvtaq_s64_f64 vcvtaq_s64_f64 |
| #define simde_vcvtaq_u16_f16 vcvtaq_u16_f16 |
| #define simde_vcvtaq_u32_f32 vcvtaq_u32_f32 |
| #define simde_vcvtaq_u64_f64 vcvtaq_u64_f64 |
| #define simde_vcvtas_s32_f32 vcvtas_s32_f32 |
| #define simde_vcvtas_u32_f32 vcvtas_u32_f32 |
| #define simde_vcvtd_f64_s64 vcvtd_f64_s64 |
| #define simde_vcvtd_f64_u64 vcvtd_f64_u64 |
| #define simde_vcvtd_n_f64_s64 vcvtd_n_f64_s64 |
| #define simde_vcvtd_n_f64_u64 vcvtd_n_f64_u64 |
| #define simde_vcvtd_n_s64_f64 vcvtd_n_s64_f64 |
| #define simde_vcvtd_n_u64_f64 vcvtd_n_u64_f64 |
| #define simde_vcvtd_s64_f64 vcvtd_s64_f64 |
| #define simde_vcvtd_u64_f64 vcvtd_u64_f64 |
| #define simde_vcvth_bf16_f32 vcvth_bf16_f32 |
| #define simde_vcvtm_u16_f16 vcvtm_u16_f16 |
| #define simde_vcvtm_u32_f32 vcvtm_u32_f32 |
| #define simde_vcvtm_u64_f64 vcvtm_u64_f64 |
| #define simde_vcvtmd_u64_f64 vcvtmd_u64_f64 |
| #define simde_vcvtmq_u16_f16 vcvtmq_u16_f16 |
| #define simde_vcvtmq_u32_f32 vcvtmq_u32_f32 |
| #define simde_vcvtmq_u64_f64 vcvtmq_u64_f64 |
| #define simde_vcvtms_u32_f32 vcvtms_u32_f32 |
| #define simde_vcvtn_s32_f32 vcvtn_s32_f32 |
| #define simde_vcvtn_s64_f64 vcvtn_s64_f64 |
| #define simde_vcvtn_u16_f16 vcvtn_u16_f16 |
| #define simde_vcvtn_u32_f32 vcvtn_u32_f32 |
| #define simde_vcvtn_u64_f64 vcvtn_u64_f64 |
| #define simde_vcvtnd_s64_f64 vcvtnd_s64_f64 |
| #define simde_vcvtnd_u64_f64 vcvtnd_u64_f64 |
| #define simde_vcvtnq_s32_f32 vcvtnq_s32_f32 |
| #define simde_vcvtnq_s64_f64 vcvtnq_s64_f64 |
| #define simde_vcvtnq_u16_f16 vcvtnq_u16_f16 |
| #define simde_vcvtnq_u32_f32 vcvtnq_u32_f32 |
| #define simde_vcvtnq_u64_f64 vcvtnq_u64_f64 |
| #define simde_vcvtns_s32_f32 vcvtns_s32_f32 |
| #define simde_vcvtns_u32_f32 vcvtns_u32_f32 |
| #define simde_vcvtp_u16_f16 vcvtp_u16_f16 |
| #define simde_vcvtp_u32_f32 vcvtp_u32_f32 |
| #define simde_vcvtp_u64_f64 vcvtp_u64_f64 |
| #define simde_vcvtpd_u64_f64 vcvtpd_u64_f64 |
| #define simde_vcvtpq_u16_f16 vcvtpq_u16_f16 |
| #define simde_vcvtpq_u32_f32 vcvtpq_u32_f32 |
| #define simde_vcvtpq_u64_f64 vcvtpq_u64_f64 |
| #define simde_vcvtps_u32_f32 vcvtps_u32_f32 |
| #define simde_vcvtq_f16_s16 vcvtq_f16_s16 |
| #define simde_vcvtq_f16_u16 vcvtq_f16_u16 |
| #define simde_vcvtq_f32_s32 vcvtq_f32_s32 |
| #define simde_vcvtq_f32_u32 vcvtq_f32_u32 |
| #define simde_vcvtq_f64_s64 vcvtq_f64_s64 |
| #define simde_vcvtq_f64_u64 vcvtq_f64_u64 |
| #define simde_vcvtq_high_bf16_f32 vcvtq_high_bf16_f32 |
| #define simde_vcvtq_high_f32_bf16 vcvtq_high_f32_bf16 |
| #define simde_vcvtq_low_bf16_f32 vcvtq_low_bf16_f32 |
| #define simde_vcvtq_low_f32_bf16 vcvtq_low_f32_bf16 |
| #define simde_vcvtq_n_f16_s16 vcvtq_n_f16_s16 |
| #define simde_vcvtq_n_f16_u16 vcvtq_n_f16_u16 |
| #define simde_vcvtq_n_f32_s32 vcvtq_n_f32_s32 |
| #define simde_vcvtq_n_f32_u32 vcvtq_n_f32_u32 |
| #define simde_vcvtq_n_f64_s64 vcvtq_n_f64_s64 |
| #define simde_vcvtq_n_f64_u64 vcvtq_n_f64_u64 |
| #define simde_vcvtq_n_s32_f32 vcvtq_n_s32_f32 |
| #define simde_vcvtq_n_s64_f64 vcvtq_n_s64_f64 |
| #define simde_vcvtq_n_u16_f16 vcvtq_n_u16_f16 |
| #define simde_vcvtq_n_u32_f32 vcvtq_n_u32_f32 |
| #define simde_vcvtq_n_u64_f64 vcvtq_n_u64_f64 |
| #define simde_vcvtq_s32_f32 vcvtq_s32_f32 |
| #define simde_vcvtq_s64_f64 vcvtq_s64_f64 |
| #define simde_vcvtq_u16_f16 vcvtq_u16_f16 |
| #define simde_vcvtq_u32_f32 vcvtq_u32_f32 |
| #define simde_vcvtq_u64_f64 vcvtq_u64_f64 |
| #define simde_vcvts_f32_s32 vcvts_f32_s32 |
| #define simde_vcvts_f32_u32 vcvts_f32_u32 |
| #define simde_vcvts_n_f32_s32 vcvts_n_f32_s32 |
| #define simde_vcvts_n_f32_u32 vcvts_n_f32_u32 |
| #define simde_vcvts_n_s32_f32 vcvts_n_s32_f32 |
| #define simde_vcvts_n_u32_f32 vcvts_n_u32_f32 |
| #define simde_vcvts_s32_f32 vcvts_s32_f32 |
| #define simde_vcvts_u32_f32 vcvts_u32_f32 |
| #define simde_vcvtx_f32_f64 vcvtx_f32_f64 |
| #define simde_vcvtx_high_f32_f64 vcvtx_high_f32_f64 |
| #define simde_vcvtxd_f32_f64 vcvtxd_f32_f64 |
| #define simde_vdiv_f16 vdiv_f16 |
| #define simde_vdiv_f32 vdiv_f32 |
| #define simde_vdiv_f64 vdiv_f64 |
| #define simde_vdivq_f16 vdivq_f16 |
| #define simde_vdivq_f32 vdivq_f32 |
| #define simde_vdivq_f64 vdivq_f64 |
| #define simde_vdot_lane_s32 vdot_lane_s32 |
| #define simde_vdot_lane_u32 vdot_lane_u32 |
| #define simde_vdot_laneq_s32 vdot_laneq_s32 |
| #define simde_vdot_laneq_u32 vdot_laneq_u32 |
| #define simde_vdot_s32 vdot_s32 |
| #define simde_vdot_u32 vdot_u32 |
| #define simde_vdotq_lane_s32 vdotq_lane_s32 |
| #define simde_vdotq_lane_u32 vdotq_lane_u32 |
| #define simde_vdotq_laneq_s32 vdotq_laneq_s32 |
| #define simde_vdotq_laneq_u32 vdotq_laneq_u32 |
| #define simde_vdotq_s32 vdotq_s32 |
| #define simde_vdotq_u32 vdotq_u32 |
| #define simde_vdup_lane_bf16 vdup_lane_bf16 |
| #define simde_vdup_lane_f16 vdup_lane_f16 |
| #define simde_vdup_lane_f32 vdup_lane_f32 |
| #define simde_vdup_lane_f64 vdup_lane_f64 |
| #define simde_vdup_lane_p16 vdup_lane_p16 |
| #define simde_vdup_lane_p64 vdup_lane_p64 |
| #define simde_vdup_lane_p8 vdup_lane_p8 |
| #define simde_vdup_lane_s16 vdup_lane_s16 |
| #define simde_vdup_lane_s32 vdup_lane_s32 |
| #define simde_vdup_lane_s64 vdup_lane_s64 |
| #define simde_vdup_lane_s8 vdup_lane_s8 |
| #define simde_vdup_lane_u16 vdup_lane_u16 |
| #define simde_vdup_lane_u32 vdup_lane_u32 |
| #define simde_vdup_lane_u64 vdup_lane_u64 |
| #define simde_vdup_lane_u8 vdup_lane_u8 |
| #define simde_vdup_laneq_bf16 vdup_laneq_bf16 |
| #define simde_vdup_laneq_f16 vdup_laneq_f16 |
| #define simde_vdup_laneq_f32 vdup_laneq_f32 |
| #define simde_vdup_laneq_f64 vdup_laneq_f64 |
| #define simde_vdup_laneq_p16 vdup_laneq_p16 |
| #define simde_vdup_laneq_p64 vdup_laneq_p64 |
| #define simde_vdup_laneq_p8 vdup_laneq_p8 |
| #define simde_vdup_laneq_s16 vdup_laneq_s16 |
| #define simde_vdup_laneq_s32 vdup_laneq_s32 |
| #define simde_vdup_laneq_s64 vdup_laneq_s64 |
| #define simde_vdup_laneq_s8 vdup_laneq_s8 |
| #define simde_vdup_laneq_u16 vdup_laneq_u16 |
| #define simde_vdup_laneq_u32 vdup_laneq_u32 |
| #define simde_vdup_laneq_u64 vdup_laneq_u64 |
| #define simde_vdup_laneq_u8 vdup_laneq_u8 |
| #define simde_vdup_n_bf16 vdup_n_bf16 |
| #define simde_vdup_n_f16 vdup_n_f16 |
| #define simde_vdup_n_f32 vdup_n_f32 |
| #define simde_vdup_n_f64 vdup_n_f64 |
| #define simde_vdup_n_p16 vdup_n_p16 |
| #define simde_vdup_n_p64 vdup_n_p64 |
| #define simde_vdup_n_p8 vdup_n_p8 |
| #define simde_vdup_n_s16 vdup_n_s16 |
| #define simde_vdup_n_s32 vdup_n_s32 |
| #define simde_vdup_n_s64 vdup_n_s64 |
| #define simde_vdup_n_s8 vdup_n_s8 |
| #define simde_vdup_n_u16 vdup_n_u16 |
| #define simde_vdup_n_u32 vdup_n_u32 |
| #define simde_vdup_n_u64 vdup_n_u64 |
| #define simde_vdup_n_u8 vdup_n_u8 |
| #define simde_vdupb_lane_p8 vdupb_lane_p8 |
| #define simde_vdupb_lane_s8 vdupb_lane_s8 |
| #define simde_vdupb_lane_u8 vdupb_lane_u8 |
| #define simde_vdupb_laneq_p8 vdupb_laneq_p8 |
| #define simde_vdupb_laneq_s8 vdupb_laneq_s8 |
| #define simde_vdupb_laneq_u8 vdupb_laneq_u8 |
| #define simde_vdupd_lane_f64 vdupd_lane_f64 |
| #define simde_vdupd_lane_s64 vdupd_lane_s64 |
| #define simde_vdupd_lane_u64 vdupd_lane_u64 |
| #define simde_vdupd_laneq_f64 vdupd_laneq_f64 |
| #define simde_vdupd_laneq_s64 vdupd_laneq_s64 |
| #define simde_vdupd_laneq_u64 vdupd_laneq_u64 |
| #define simde_vduph_lane_bf16 vduph_lane_bf16 |
| #define simde_vduph_lane_f16 vduph_lane_f16 |
| #define simde_vduph_lane_p16 vduph_lane_p16 |
| #define simde_vduph_lane_s16 vduph_lane_s16 |
| #define simde_vduph_lane_u16 vduph_lane_u16 |
| #define simde_vduph_laneq_bf16 vduph_laneq_bf16 |
| #define simde_vduph_laneq_f16 vduph_laneq_f16 |
| #define simde_vduph_laneq_p16 vduph_laneq_p16 |
| #define simde_vduph_laneq_s16 vduph_laneq_s16 |
| #define simde_vduph_laneq_u16 vduph_laneq_u16 |
| #define simde_vdupq_lane_bf16 vdupq_lane_bf16 |
| #define simde_vdupq_lane_f16 vdupq_lane_f16 |
| #define simde_vdupq_lane_f32 vdupq_lane_f32 |
| #define simde_vdupq_lane_f64 vdupq_lane_f64 |
| #define simde_vdupq_lane_p16 vdupq_lane_p16 |
| #define simde_vdupq_lane_p64 vdupq_lane_p64 |
| #define simde_vdupq_lane_p8 vdupq_lane_p8 |
| #define simde_vdupq_lane_s16 vdupq_lane_s16 |
| #define simde_vdupq_lane_s32 vdupq_lane_s32 |
| #define simde_vdupq_lane_s64 vdupq_lane_s64 |
| #define simde_vdupq_lane_s8 vdupq_lane_s8 |
| #define simde_vdupq_lane_u16 vdupq_lane_u16 |
| #define simde_vdupq_lane_u32 vdupq_lane_u32 |
| #define simde_vdupq_lane_u64 vdupq_lane_u64 |
| #define simde_vdupq_lane_u8 vdupq_lane_u8 |
| #define simde_vdupq_laneq_bf16 vdupq_laneq_bf16 |
| #define simde_vdupq_laneq_f16 vdupq_laneq_f16 |
| #define simde_vdupq_laneq_f32 vdupq_laneq_f32 |
| #define simde_vdupq_laneq_f64 vdupq_laneq_f64 |
| #define simde_vdupq_laneq_p16 vdupq_laneq_p16 |
| #define simde_vdupq_laneq_p64 vdupq_laneq_p64 |
| #define simde_vdupq_laneq_p8 vdupq_laneq_p8 |
| #define simde_vdupq_laneq_s16 vdupq_laneq_s16 |
| #define simde_vdupq_laneq_s32 vdupq_laneq_s32 |
| #define simde_vdupq_laneq_s64 vdupq_laneq_s64 |
| #define simde_vdupq_laneq_s8 vdupq_laneq_s8 |
| #define simde_vdupq_laneq_u16 vdupq_laneq_u16 |
| #define simde_vdupq_laneq_u32 vdupq_laneq_u32 |
| #define simde_vdupq_laneq_u64 vdupq_laneq_u64 |
| #define simde_vdupq_laneq_u8 vdupq_laneq_u8 |
| #define simde_vdupq_n_bf16 vdupq_n_bf16 |
| #define simde_vdupq_n_f16 vdupq_n_f16 |
| #define simde_vdupq_n_f32 vdupq_n_f32 |
| #define simde_vdupq_n_f64 vdupq_n_f64 |
| #define simde_vdupq_n_p16 vdupq_n_p16 |
| #define simde_vdupq_n_p64 vdupq_n_p64 |
| #define simde_vdupq_n_p8 vdupq_n_p8 |
| #define simde_vdupq_n_s16 vdupq_n_s16 |
| #define simde_vdupq_n_s32 vdupq_n_s32 |
| #define simde_vdupq_n_s64 vdupq_n_s64 |
| #define simde_vdupq_n_s8 vdupq_n_s8 |
| #define simde_vdupq_n_u16 vdupq_n_u16 |
| #define simde_vdupq_n_u32 vdupq_n_u32 |
| #define simde_vdupq_n_u64 vdupq_n_u64 |
| #define simde_vdupq_n_u8 vdupq_n_u8 |
| #define simde_vdups_lane_f32 vdups_lane_f32 |
| #define simde_vdups_lane_s32 vdups_lane_s32 |
| #define simde_vdups_lane_u32 vdups_lane_u32 |
| #define simde_vdups_laneq_f32 vdups_laneq_f32 |
| #define simde_vdups_laneq_s32 vdups_laneq_s32 |
| #define simde_vdups_laneq_u32 vdups_laneq_u32 |
| #define simde_veor_s16 veor_s16 |
| #define simde_veor_s32 veor_s32 |
| #define simde_veor_s64 veor_s64 |
| #define simde_veor_s8 veor_s8 |
| #define simde_veor_u16 veor_u16 |
| #define simde_veor_u32 veor_u32 |
| #define simde_veor_u64 veor_u64 |
| #define simde_veor_u8 veor_u8 |
| #define simde_veor3q_s16 veor3q_s16 |
| #define simde_veor3q_s32 veor3q_s32 |
| #define simde_veor3q_s64 veor3q_s64 |
| #define simde_veor3q_s8 veor3q_s8 |
| #define simde_veor3q_u16 veor3q_u16 |
| #define simde_veor3q_u32 veor3q_u32 |
| #define simde_veor3q_u64 veor3q_u64 |
| #define simde_veor3q_u8 veor3q_u8 |
| #define simde_veorq_s16 veorq_s16 |
| #define simde_veorq_s32 veorq_s32 |
| #define simde_veorq_s64 veorq_s64 |
| #define simde_veorq_s8 veorq_s8 |
| #define simde_veorq_u16 veorq_u16 |
| #define simde_veorq_u32 veorq_u32 |
| #define simde_veorq_u64 veorq_u64 |
| #define simde_veorq_u8 veorq_u8 |
| #define simde_vext_f16 vext_f16 |
| #define simde_vext_f32 vext_f32 |
| #define simde_vext_f64 vext_f64 |
| #define simde_vext_p16 vext_p16 |
| #define simde_vext_p64 vext_p64 |
| #define simde_vext_p8 vext_p8 |
| #define simde_vext_s16 vext_s16 |
| #define simde_vext_s32 vext_s32 |
| #define simde_vext_s64 vext_s64 |
| #define simde_vext_s8 vext_s8 |
| #define simde_vext_u16 vext_u16 |
| #define simde_vext_u32 vext_u32 |
| #define simde_vext_u64 vext_u64 |
| #define simde_vext_u8 vext_u8 |
| #define simde_vextq_f16 vextq_f16 |
| #define simde_vextq_f32 vextq_f32 |
| #define simde_vextq_f64 vextq_f64 |
| #define simde_vextq_p16 vextq_p16 |
| #define simde_vextq_p64 vextq_p64 |
| #define simde_vextq_p8 vextq_p8 |
| #define simde_vextq_s16 vextq_s16 |
| #define simde_vextq_s32 vextq_s32 |
| #define simde_vextq_s64 vextq_s64 |
| #define simde_vextq_s8 vextq_s8 |
| #define simde_vextq_u16 vextq_u16 |
| #define simde_vextq_u32 vextq_u32 |
| #define simde_vextq_u64 vextq_u64 |
| #define simde_vextq_u8 vextq_u8 |
| #define simde_vfma_f16 vfma_f16 |
| #define simde_vfma_f32 vfma_f32 |
| #define simde_vfma_f64 vfma_f64 |
| #define simde_vfma_lane_f16 vfma_lane_f16 |
| #define simde_vfma_lane_f32 vfma_lane_f32 |
| #define simde_vfma_lane_f64 vfma_lane_f64 |
| #define simde_vfma_laneq_f16 vfma_laneq_f16 |
| #define simde_vfma_laneq_f32 vfma_laneq_f32 |
| #define simde_vfma_laneq_f64 vfma_laneq_f64 |
| #define simde_vfma_n_f16 vfma_n_f16 |
| #define simde_vfma_n_f32 vfma_n_f32 |
| #define simde_vfma_n_f64 vfma_n_f64 |
| #define simde_vfmad_lane_f64 vfmad_lane_f64 |
| #define simde_vfmad_laneq_f64 vfmad_laneq_f64 |
| #define simde_vfmah_lane_f16 vfmah_lane_f16 |
| #define simde_vfmah_laneq_f16 vfmah_laneq_f16 |
| #define simde_vfmaq_f16 vfmaq_f16 |
| #define simde_vfmaq_f32 vfmaq_f32 |
| #define simde_vfmaq_f64 vfmaq_f64 |
| #define simde_vfmaq_lane_f16 vfmaq_lane_f16 |
| #define simde_vfmaq_lane_f32 vfmaq_lane_f32 |
| #define simde_vfmaq_lane_f64 vfmaq_lane_f64 |
| #define simde_vfmaq_laneq_f16 vfmaq_laneq_f16 |
| #define simde_vfmaq_laneq_f32 vfmaq_laneq_f32 |
| #define simde_vfmaq_laneq_f64 vfmaq_laneq_f64 |
| #define simde_vfmaq_n_f16 vfmaq_n_f16 |
| #define simde_vfmaq_n_f32 vfmaq_n_f32 |
| #define simde_vfmaq_n_f64 vfmaq_n_f64 |
| #define simde_vfmas_lane_f32 vfmas_lane_f32 |
| #define simde_vfmas_laneq_f32 vfmas_laneq_f32 |
| #define simde_vfmlal_high_f16 vfmlal_high_f16 |
| #define simde_vfmlal_lane_high_f16 vfmlal_lane_high_f16 |
| #define simde_vfmlal_lane_low_f16 vfmlal_lane_low_f16 |
| #define simde_vfmlal_laneq_high_f16 vfmlal_laneq_high_f16 |
| #define simde_vfmlal_laneq_low_f16 vfmlal_laneq_low_f16 |
| #define simde_vfmlal_low_f16 vfmlal_low_f16 |
| #define simde_vfmlalq_high_f16 vfmlalq_high_f16 |
| #define simde_vfmlalq_lane_high_f16 vfmlalq_lane_high_f16 |
| #define simde_vfmlalq_lane_low_f16 vfmlalq_lane_low_f16 |
| #define simde_vfmlalq_laneq_high_f16 vfmlalq_laneq_high_f16 |
| #define simde_vfmlalq_laneq_low_f16 vfmlalq_laneq_low_f16 |
| #define simde_vfmlalq_low_f16 vfmlalq_low_f16 |
| #define simde_vfmlsl_high_f16 vfmlsl_high_f16 |
| #define simde_vfmlsl_lane_high_f16 vfmlsl_lane_high_f16 |
| #define simde_vfmlsl_lane_low_f16 vfmlsl_lane_low_f16 |
| #define simde_vfmlsl_laneq_high_f16 vfmlsl_laneq_high_f16 |
| #define simde_vfmlsl_laneq_low_f16 vfmlsl_laneq_low_f16 |
| #define simde_vfmlsl_low_f16 vfmlsl_low_f16 |
| #define simde_vfmlslq_high_f16 vfmlslq_high_f16 |
| #define simde_vfmlslq_lane_high_f16 vfmlslq_lane_high_f16 |
| #define simde_vfmlslq_lane_low_f16 vfmlslq_lane_low_f16 |
| #define simde_vfmlslq_laneq_high_f16 vfmlslq_laneq_high_f16 |
| #define simde_vfmlslq_laneq_low_f16 vfmlslq_laneq_low_f16 |
| #define simde_vfmlslq_low_f16 vfmlslq_low_f16 |
| #define simde_vfms_f16 vfms_f16 |
| #define simde_vfms_f32 vfms_f32 |
| #define simde_vfms_f64 vfms_f64 |
| #define simde_vfms_lane_f16 vfms_lane_f16 |
| #define simde_vfms_lane_f32 vfms_lane_f32 |
| #define simde_vfms_lane_f64 vfms_lane_f64 |
| #define simde_vfms_laneq_f16 vfms_laneq_f16 |
| #define simde_vfms_laneq_f32 vfms_laneq_f32 |
| #define simde_vfms_laneq_f64 vfms_laneq_f64 |
| #define simde_vfms_n_f16 vfms_n_f16 |
| #define simde_vfms_n_f32 vfms_n_f32 |
| #define simde_vfms_n_f64 vfms_n_f64 |
| #define simde_vfmsd_lane_f64 vfmsd_lane_f64 |
| #define simde_vfmsd_laneq_f64 vfmsd_laneq_f64 |
| #define simde_vfmsh_lane_f16 vfmsh_lane_f16 |
| #define simde_vfmsh_laneq_f16 vfmsh_laneq_f16 |
| #define simde_vfmsq_f16 vfmsq_f16 |
| #define simde_vfmsq_f32 vfmsq_f32 |
| #define simde_vfmsq_f64 vfmsq_f64 |
| #define simde_vfmsq_lane_f16 vfmsq_lane_f16 |
| #define simde_vfmsq_lane_f32 vfmsq_lane_f32 |
| #define simde_vfmsq_lane_f64 vfmsq_lane_f64 |
| #define simde_vfmsq_laneq_f16 vfmsq_laneq_f16 |
| #define simde_vfmsq_laneq_f32 vfmsq_laneq_f32 |
| #define simde_vfmsq_laneq_f64 vfmsq_laneq_f64 |
| #define simde_vfmsq_n_f16 vfmsq_n_f16 |
| #define simde_vfmsq_n_f32 vfmsq_n_f32 |
| #define simde_vfmsq_n_f64 vfmsq_n_f64 |
| #define simde_vfmss_lane_f32 vfmss_lane_f32 |
| #define simde_vfmss_laneq_f32 vfmss_laneq_f32 |
| #define simde_vget_high_bf16 vget_high_bf16 |
| #define simde_vget_high_f16 vget_high_f16 |
| #define simde_vget_high_f32 vget_high_f32 |
| #define simde_vget_high_f64 vget_high_f64 |
| #define simde_vget_high_p16 vget_high_p16 |
| #define simde_vget_high_p64 vget_high_p64 |
| #define simde_vget_high_p8 vget_high_p8 |
| #define simde_vget_high_s16 vget_high_s16 |
| #define simde_vget_high_s32 vget_high_s32 |
| #define simde_vget_high_s64 vget_high_s64 |
| #define simde_vget_high_s8 vget_high_s8 |
| #define simde_vget_high_u16 vget_high_u16 |
| #define simde_vget_high_u32 vget_high_u32 |
| #define simde_vget_high_u64 vget_high_u64 |
| #define simde_vget_high_u8 vget_high_u8 |
| #define simde_vget_lane_bf16 vget_lane_bf16 |
| #define simde_vget_lane_f16 vget_lane_f16 |
| #define simde_vget_lane_f32 vget_lane_f32 |
| #define simde_vget_lane_f64 vget_lane_f64 |
| #define simde_vget_lane_p16 vget_lane_p16 |
| #define simde_vget_lane_p64 vget_lane_p64 |
| #define simde_vget_lane_p8 vget_lane_p8 |
| #define simde_vget_lane_s16 vget_lane_s16 |
| #define simde_vget_lane_s32 vget_lane_s32 |
| #define simde_vget_lane_s64 vget_lane_s64 |
| #define simde_vget_lane_s8 vget_lane_s8 |
| #define simde_vget_lane_u16 vget_lane_u16 |
| #define simde_vget_lane_u32 vget_lane_u32 |
| #define simde_vget_lane_u64 vget_lane_u64 |
| #define simde_vget_lane_u8 vget_lane_u8 |
| #define simde_vget_low_bf16 vget_low_bf16 |
| #define simde_vget_low_f16 vget_low_f16 |
| #define simde_vget_low_f32 vget_low_f32 |
| #define simde_vget_low_f64 vget_low_f64 |
| #define simde_vget_low_p16 vget_low_p16 |
| #define simde_vget_low_p64 vget_low_p64 |
| #define simde_vget_low_p8 vget_low_p8 |
| #define simde_vget_low_s16 vget_low_s16 |
| #define simde_vget_low_s32 vget_low_s32 |
| #define simde_vget_low_s64 vget_low_s64 |
| #define simde_vget_low_s8 vget_low_s8 |
| #define simde_vget_low_u16 vget_low_u16 |
| #define simde_vget_low_u32 vget_low_u32 |
| #define simde_vget_low_u64 vget_low_u64 |
| #define simde_vget_low_u8 vget_low_u8 |
| #define simde_vgetq_lane_bf16 vgetq_lane_bf16 |
| #define simde_vgetq_lane_f16 vgetq_lane_f16 |
| #define simde_vgetq_lane_f32 vgetq_lane_f32 |
| #define simde_vgetq_lane_f64 vgetq_lane_f64 |
| #define simde_vgetq_lane_p16 vgetq_lane_p16 |
| #define simde_vgetq_lane_p64 vgetq_lane_p64 |
| #define simde_vgetq_lane_p8 vgetq_lane_p8 |
| #define simde_vgetq_lane_s16 vgetq_lane_s16 |
| #define simde_vgetq_lane_s32 vgetq_lane_s32 |
| #define simde_vgetq_lane_s64 vgetq_lane_s64 |
| #define simde_vgetq_lane_s8 vgetq_lane_s8 |
| #define simde_vgetq_lane_u16 vgetq_lane_u16 |
| #define simde_vgetq_lane_u32 vgetq_lane_u32 |
| #define simde_vgetq_lane_u64 vgetq_lane_u64 |
| #define simde_vgetq_lane_u8 vgetq_lane_u8 |
| #define simde_vhadd_s16 vhadd_s16 |
| #define simde_vhadd_s32 vhadd_s32 |
| #define simde_vhadd_s8 vhadd_s8 |
| #define simde_vhadd_u16 vhadd_u16 |
| #define simde_vhadd_u32 vhadd_u32 |
| #define simde_vhadd_u8 vhadd_u8 |
| #define simde_vhaddq_s16 vhaddq_s16 |
| #define simde_vhaddq_s32 vhaddq_s32 |
| #define simde_vhaddq_s8 vhaddq_s8 |
| #define simde_vhaddq_u16 vhaddq_u16 |
| #define simde_vhaddq_u32 vhaddq_u32 |
| #define simde_vhaddq_u8 vhaddq_u8 |
| #define simde_vhsub_s16 vhsub_s16 |
| #define simde_vhsub_s32 vhsub_s32 |
| #define simde_vhsub_s8 vhsub_s8 |
| #define simde_vhsub_u16 vhsub_u16 |
| #define simde_vhsub_u32 vhsub_u32 |
| #define simde_vhsub_u8 vhsub_u8 |
| #define simde_vhsubq_s16 vhsubq_s16 |
| #define simde_vhsubq_s32 vhsubq_s32 |
| #define simde_vhsubq_s8 vhsubq_s8 |
| #define simde_vhsubq_u16 vhsubq_u16 |
| #define simde_vhsubq_u32 vhsubq_u32 |
| #define simde_vhsubq_u8 vhsubq_u8 |
| #define simde_vld1_bf16 vld1_bf16 |
| #define simde_vld1_bf16_x2 vld1_bf16_x2 |
| #define simde_vld1_bf16_x3 vld1_bf16_x3 |
| #define simde_vld1_bf16_x4 vld1_bf16_x4 |
| #define simde_vld1_dup_bf16 vld1_dup_bf16 |
| #define simde_vld1_dup_f16 vld1_dup_f16 |
| #define simde_vld1_dup_f32 vld1_dup_f32 |
| #define simde_vld1_dup_f64 vld1_dup_f64 |
| #define simde_vld1_dup_p16 vld1_dup_p16 |
| #define simde_vld1_dup_p64 vld1_dup_p64 |
| #define simde_vld1_dup_p8 vld1_dup_p8 |
| #define simde_vld1_dup_s16 vld1_dup_s16 |
| #define simde_vld1_dup_s32 vld1_dup_s32 |
| #define simde_vld1_dup_s64 vld1_dup_s64 |
| #define simde_vld1_dup_s8 vld1_dup_s8 |
| #define simde_vld1_dup_u16 vld1_dup_u16 |
| #define simde_vld1_dup_u32 vld1_dup_u32 |
| #define simde_vld1_dup_u64 vld1_dup_u64 |
| #define simde_vld1_dup_u8 vld1_dup_u8 |
| #define simde_vld1_f16 vld1_f16 |
| #define simde_vld1_f16_x2 vld1_f16_x2 |
| #define simde_vld1_f16_x3 vld1_f16_x3 |
| #define simde_vld1_f16_x4 vld1_f16_x4 |
| #define simde_vld1_f32 vld1_f32 |
| #define simde_vld1_f32_x2 vld1_f32_x2 |
| #define simde_vld1_f32_x3 vld1_f32_x3 |
| #define simde_vld1_f32_x4 vld1_f32_x4 |
| #define simde_vld1_f64 vld1_f64 |
| #define simde_vld1_f64_x2 vld1_f64_x2 |
| #define simde_vld1_f64_x3 vld1_f64_x3 |
| #define simde_vld1_f64_x4 vld1_f64_x4 |
| #define simde_vld1_lane_bf16 vld1_lane_bf16 |
| #define simde_vld1_lane_f16 vld1_lane_f16 |
| #define simde_vld1_lane_f32 vld1_lane_f32 |
| #define simde_vld1_lane_f64 vld1_lane_f64 |
| #define simde_vld1_lane_p16 vld1_lane_p16 |
| #define simde_vld1_lane_p64 vld1_lane_p64 |
| #define simde_vld1_lane_p8 vld1_lane_p8 |
| #define simde_vld1_lane_s16 vld1_lane_s16 |
| #define simde_vld1_lane_s32 vld1_lane_s32 |
| #define simde_vld1_lane_s64 vld1_lane_s64 |
| #define simde_vld1_lane_s8 vld1_lane_s8 |
| #define simde_vld1_lane_u16 vld1_lane_u16 |
| #define simde_vld1_lane_u32 vld1_lane_u32 |
| #define simde_vld1_lane_u64 vld1_lane_u64 |
| #define simde_vld1_lane_u8 vld1_lane_u8 |
| #define simde_vld1_p16 vld1_p16 |
| #define simde_vld1_p16_x2 vld1_p16_x2 |
| #define simde_vld1_p16_x3 vld1_p16_x3 |
| #define simde_vld1_p16_x4 vld1_p16_x4 |
| #define simde_vld1_p64 vld1_p64 |
| #define simde_vld1_p64_x2 vld1_p64_x2 |
| #define simde_vld1_p64_x3 vld1_p64_x3 |
| #define simde_vld1_p64_x4 vld1_p64_x4 |
| #define simde_vld1_p8 vld1_p8 |
| #define simde_vld1_p8_x2 vld1_p8_x2 |
| #define simde_vld1_p8_x3 vld1_p8_x3 |
| #define simde_vld1_p8_x4 vld1_p8_x4 |
| #define simde_vld1_s16 vld1_s16 |
| #define simde_vld1_s16_x2 vld1_s16_x2 |
| #define simde_vld1_s16_x3 vld1_s16_x3 |
| #define simde_vld1_s16_x4 vld1_s16_x4 |
| #define simde_vld1_s32 vld1_s32 |
| #define simde_vld1_s32_x2 vld1_s32_x2 |
| #define simde_vld1_s32_x3 vld1_s32_x3 |
| #define simde_vld1_s32_x4 vld1_s32_x4 |
| #define simde_vld1_s64 vld1_s64 |
| #define simde_vld1_s64_x2 vld1_s64_x2 |
| #define simde_vld1_s64_x3 vld1_s64_x3 |
| #define simde_vld1_s64_x4 vld1_s64_x4 |
| #define simde_vld1_s8 vld1_s8 |
| #define simde_vld1_s8_x2 vld1_s8_x2 |
| #define simde_vld1_s8_x3 vld1_s8_x3 |
| #define simde_vld1_s8_x4 vld1_s8_x4 |
| #define simde_vld1_u16 vld1_u16 |
| #define simde_vld1_u16_x2 vld1_u16_x2 |
| #define simde_vld1_u16_x3 vld1_u16_x3 |
| #define simde_vld1_u16_x4 vld1_u16_x4 |
| #define simde_vld1_u32 vld1_u32 |
| #define simde_vld1_u32_x2 vld1_u32_x2 |
| #define simde_vld1_u32_x3 vld1_u32_x3 |
| #define simde_vld1_u32_x4 vld1_u32_x4 |
| #define simde_vld1_u64 vld1_u64 |
| #define simde_vld1_u64_x2 vld1_u64_x2 |
| #define simde_vld1_u64_x3 vld1_u64_x3 |
| #define simde_vld1_u64_x4 vld1_u64_x4 |
| #define simde_vld1_u8 vld1_u8 |
| #define simde_vld1_u8_x2 vld1_u8_x2 |
| #define simde_vld1_u8_x3 vld1_u8_x3 |
| #define simde_vld1_u8_x4 vld1_u8_x4 |
| #define simde_vld1q_bf16 vld1q_bf16 |
| #define simde_vld1q_bf16_x2 vld1q_bf16_x2 |
| #define simde_vld1q_bf16_x3 vld1q_bf16_x3 |
| #define simde_vld1q_bf16_x4 vld1q_bf16_x4 |
| #define simde_vld1q_dup_bf16 vld1q_dup_bf16 |
| #define simde_vld1q_dup_f16 vld1q_dup_f16 |
| #define simde_vld1q_dup_f32 vld1q_dup_f32 |
| #define simde_vld1q_dup_f64 vld1q_dup_f64 |
| #define simde_vld1q_dup_p16 vld1q_dup_p16 |
| #define simde_vld1q_dup_p64 vld1q_dup_p64 |
| #define simde_vld1q_dup_p8 vld1q_dup_p8 |
| #define simde_vld1q_dup_s16 vld1q_dup_s16 |
| #define simde_vld1q_dup_s32 vld1q_dup_s32 |
| #define simde_vld1q_dup_s64 vld1q_dup_s64 |
| #define simde_vld1q_dup_s8 vld1q_dup_s8 |
| #define simde_vld1q_dup_u16 vld1q_dup_u16 |
| #define simde_vld1q_dup_u32 vld1q_dup_u32 |
| #define simde_vld1q_dup_u64 vld1q_dup_u64 |
| #define simde_vld1q_dup_u8 vld1q_dup_u8 |
| #define simde_vld1q_f16 vld1q_f16 |
| #define simde_vld1q_f16_x2 vld1q_f16_x2 |
| #define simde_vld1q_f16_x3 vld1q_f16_x3 |
| #define simde_vld1q_f16_x4 vld1q_f16_x4 |
| #define simde_vld1q_f32 vld1q_f32 |
| #define simde_vld1q_f32_x2 vld1q_f32_x2 |
| #define simde_vld1q_f32_x3 vld1q_f32_x3 |
| #define simde_vld1q_f32_x4 vld1q_f32_x4 |
| #define simde_vld1q_f64 vld1q_f64 |
| #define simde_vld1q_f64_x2 vld1q_f64_x2 |
| #define simde_vld1q_f64_x3 vld1q_f64_x3 |
| #define simde_vld1q_f64_x4 vld1q_f64_x4 |
| #define simde_vld1q_lane_bf16 vld1q_lane_bf16 |
| #define simde_vld1q_lane_f16 vld1q_lane_f16 |
| #define simde_vld1q_lane_f32 vld1q_lane_f32 |
| #define simde_vld1q_lane_f64 vld1q_lane_f64 |
| #define simde_vld1q_lane_p16 vld1q_lane_p16 |
| #define simde_vld1q_lane_p64 vld1q_lane_p64 |
| #define simde_vld1q_lane_p8 vld1q_lane_p8 |
| #define simde_vld1q_lane_s16 vld1q_lane_s16 |
| #define simde_vld1q_lane_s32 vld1q_lane_s32 |
| #define simde_vld1q_lane_s64 vld1q_lane_s64 |
| #define simde_vld1q_lane_s8 vld1q_lane_s8 |
| #define simde_vld1q_lane_u16 vld1q_lane_u16 |
| #define simde_vld1q_lane_u32 vld1q_lane_u32 |
| #define simde_vld1q_lane_u64 vld1q_lane_u64 |
| #define simde_vld1q_lane_u8 vld1q_lane_u8 |
| #define simde_vld1q_p16 vld1q_p16 |
| #define simde_vld1q_p16_x2 vld1q_p16_x2 |
| #define simde_vld1q_p16_x3 vld1q_p16_x3 |
| #define simde_vld1q_p16_x4 vld1q_p16_x4 |
| #define simde_vld1q_p64 vld1q_p64 |
| #define simde_vld1q_p64_x2 vld1q_p64_x2 |
| #define simde_vld1q_p64_x3 vld1q_p64_x3 |
| #define simde_vld1q_p64_x4 vld1q_p64_x4 |
| #define simde_vld1q_p8 vld1q_p8 |
| #define simde_vld1q_p8_x2 vld1q_p8_x2 |
| #define simde_vld1q_p8_x3 vld1q_p8_x3 |
| #define simde_vld1q_p8_x4 vld1q_p8_x4 |
| #define simde_vld1q_s16 vld1q_s16 |
| #define simde_vld1q_s16_x2 vld1q_s16_x2 |
| #define simde_vld1q_s16_x3 vld1q_s16_x3 |
| #define simde_vld1q_s16_x4 vld1q_s16_x4 |
| #define simde_vld1q_s32 vld1q_s32 |
| #define simde_vld1q_s32_x2 vld1q_s32_x2 |
| #define simde_vld1q_s32_x3 vld1q_s32_x3 |
| #define simde_vld1q_s32_x4 vld1q_s32_x4 |
| #define simde_vld1q_s64 vld1q_s64 |
| #define simde_vld1q_s64_x2 vld1q_s64_x2 |
| #define simde_vld1q_s64_x3 vld1q_s64_x3 |
| #define simde_vld1q_s64_x4 vld1q_s64_x4 |
| #define simde_vld1q_s8 vld1q_s8 |
| #define simde_vld1q_s8_x2 vld1q_s8_x2 |
| #define simde_vld1q_s8_x3 vld1q_s8_x3 |
| #define simde_vld1q_s8_x4 vld1q_s8_x4 |
| #define simde_vld1q_u16 vld1q_u16 |
| #define simde_vld1q_u16_x2 vld1q_u16_x2 |
| #define simde_vld1q_u16_x3 vld1q_u16_x3 |
| #define simde_vld1q_u16_x4 vld1q_u16_x4 |
| #define simde_vld1q_u32 vld1q_u32 |
| #define simde_vld1q_u32_x2 vld1q_u32_x2 |
| #define simde_vld1q_u32_x3 vld1q_u32_x3 |
| #define simde_vld1q_u32_x4 vld1q_u32_x4 |
| #define simde_vld1q_u64 vld1q_u64 |
| #define simde_vld1q_u64_x2 vld1q_u64_x2 |
| #define simde_vld1q_u64_x3 vld1q_u64_x3 |
| #define simde_vld1q_u64_x4 vld1q_u64_x4 |
| #define simde_vld1q_u8 vld1q_u8 |
| #define simde_vld1q_u8_x2 vld1q_u8_x2 |
| #define simde_vld1q_u8_x3 vld1q_u8_x3 |
| #define simde_vld1q_u8_x4 vld1q_u8_x4 |
| #define simde_vld2_bf16 vld2_bf16 |
| #define simde_vld2_dup_bf16 vld2_dup_bf16 |
| #define simde_vld2_dup_f16 vld2_dup_f16 |
| #define simde_vld2_dup_f32 vld2_dup_f32 |
| #define simde_vld2_dup_f64 vld2_dup_f64 |
| #define simde_vld2_dup_p16 vld2_dup_p16 |
| #define simde_vld2_dup_p64 vld2_dup_p64 |
| #define simde_vld2_dup_p8 vld2_dup_p8 |
| #define simde_vld2_dup_s16 vld2_dup_s16 |
| #define simde_vld2_dup_s32 vld2_dup_s32 |
| #define simde_vld2_dup_s64 vld2_dup_s64 |
| #define simde_vld2_dup_s8 vld2_dup_s8 |
| #define simde_vld2_dup_u16 vld2_dup_u16 |
| #define simde_vld2_dup_u32 vld2_dup_u32 |
| #define simde_vld2_dup_u64 vld2_dup_u64 |
| #define simde_vld2_dup_u8 vld2_dup_u8 |
| #define simde_vld2_f16 vld2_f16 |
| #define simde_vld2_f32 vld2_f32 |
| #define simde_vld2_f64 vld2_f64 |
| #define simde_vld2_lane_bf16 vld2_lane_bf16 |
| #define simde_vld2_lane_f16 vld2_lane_f16 |
| #define simde_vld2_lane_f32 vld2_lane_f32 |
| #define simde_vld2_lane_f64 vld2_lane_f64 |
| #define simde_vld2_lane_p16 vld2_lane_p16 |
| #define simde_vld2_lane_p64 vld2_lane_p64 |
| #define simde_vld2_lane_p8 vld2_lane_p8 |
| #define simde_vld2_lane_s16 vld2_lane_s16 |
| #define simde_vld2_lane_s32 vld2_lane_s32 |
| #define simde_vld2_lane_s64 vld2_lane_s64 |
| #define simde_vld2_lane_s8 vld2_lane_s8 |
| #define simde_vld2_lane_u16 vld2_lane_u16 |
| #define simde_vld2_lane_u32 vld2_lane_u32 |
| #define simde_vld2_lane_u64 vld2_lane_u64 |
| #define simde_vld2_lane_u8 vld2_lane_u8 |
| #define simde_vld2_p16 vld2_p16 |
| #define simde_vld2_p64 vld2_p64 |
| #define simde_vld2_p8 vld2_p8 |
| #define simde_vld2_s16 vld2_s16 |
| #define simde_vld2_s32 vld2_s32 |
| #define simde_vld2_s64 vld2_s64 |
| #define simde_vld2_s8 vld2_s8 |
| #define simde_vld2_u16 vld2_u16 |
| #define simde_vld2_u32 vld2_u32 |
| #define simde_vld2_u64 vld2_u64 |
| #define simde_vld2_u8 vld2_u8 |
| #define simde_vld2q_bf16 vld2q_bf16 |
| #define simde_vld2q_dup_bf16 vld2q_dup_bf16 |
| #define simde_vld2q_dup_f16 vld2q_dup_f16 |
| #define simde_vld2q_dup_f32 vld2q_dup_f32 |
| #define simde_vld2q_dup_f64 vld2q_dup_f64 |
| #define simde_vld2q_dup_p16 vld2q_dup_p16 |
| #define simde_vld2q_dup_p64 vld2q_dup_p64 |
| #define simde_vld2q_dup_p8 vld2q_dup_p8 |
| #define simde_vld2q_dup_s16 vld2q_dup_s16 |
| #define simde_vld2q_dup_s32 vld2q_dup_s32 |
| #define simde_vld2q_dup_s64 vld2q_dup_s64 |
| #define simde_vld2q_dup_s8 vld2q_dup_s8 |
| #define simde_vld2q_dup_u16 vld2q_dup_u16 |
| #define simde_vld2q_dup_u32 vld2q_dup_u32 |
| #define simde_vld2q_dup_u64 vld2q_dup_u64 |
| #define simde_vld2q_dup_u8 vld2q_dup_u8 |
| #define simde_vld2q_f16 vld2q_f16 |
| #define simde_vld2q_f32 vld2q_f32 |
| #define simde_vld2q_f64 vld2q_f64 |
| #define simde_vld2q_lane_bf16 vld2q_lane_bf16 |
| #define simde_vld2q_lane_f16 vld2q_lane_f16 |
| #define simde_vld2q_lane_f32 vld2q_lane_f32 |
| #define simde_vld2q_lane_f64 vld2q_lane_f64 |
| #define simde_vld2q_lane_p16 vld2q_lane_p16 |
| #define simde_vld2q_lane_p64 vld2q_lane_p64 |
| #define simde_vld2q_lane_p8 vld2q_lane_p8 |
| #define simde_vld2q_lane_s16 vld2q_lane_s16 |
| #define simde_vld2q_lane_s32 vld2q_lane_s32 |
| #define simde_vld2q_lane_s64 vld2q_lane_s64 |
| #define simde_vld2q_lane_s8 vld2q_lane_s8 |
| #define simde_vld2q_lane_u16 vld2q_lane_u16 |
| #define simde_vld2q_lane_u32 vld2q_lane_u32 |
| #define simde_vld2q_lane_u64 vld2q_lane_u64 |
| #define simde_vld2q_lane_u8 vld2q_lane_u8 |
| #define simde_vld2q_p16 vld2q_p16 |
| #define simde_vld2q_p64 vld2q_p64 |
| #define simde_vld2q_p8 vld2q_p8 |
| #define simde_vld2q_s16 vld2q_s16 |
| #define simde_vld2q_s32 vld2q_s32 |
| #define simde_vld2q_s64 vld2q_s64 |
| #define simde_vld2q_s8 vld2q_s8 |
| #define simde_vld2q_u16 vld2q_u16 |
| #define simde_vld2q_u32 vld2q_u32 |
| #define simde_vld2q_u64 vld2q_u64 |
| #define simde_vld2q_u8 vld2q_u8 |
| #define simde_vld3_bf16 vld3_bf16 |
| #define simde_vld3_dup_bf16 vld3_dup_bf16 |
| #define simde_vld3_dup_f16 vld3_dup_f16 |
| #define simde_vld3_dup_f32 vld3_dup_f32 |
| #define simde_vld3_dup_f64 vld3_dup_f64 |
| #define simde_vld3_dup_p16 vld3_dup_p16 |
| #define simde_vld3_dup_p64 vld3_dup_p64 |
| #define simde_vld3_dup_p8 vld3_dup_p8 |
| #define simde_vld3_dup_s16 vld3_dup_s16 |
| #define simde_vld3_dup_s32 vld3_dup_s32 |
| #define simde_vld3_dup_s64 vld3_dup_s64 |
| #define simde_vld3_dup_s8 vld3_dup_s8 |
| #define simde_vld3_dup_u16 vld3_dup_u16 |
| #define simde_vld3_dup_u32 vld3_dup_u32 |
| #define simde_vld3_dup_u64 vld3_dup_u64 |
| #define simde_vld3_dup_u8 vld3_dup_u8 |
| #define simde_vld3_f16 vld3_f16 |
| #define simde_vld3_f32 vld3_f32 |
| #define simde_vld3_f64 vld3_f64 |
| #define simde_vld3_lane_bf16 vld3_lane_bf16 |
| #define simde_vld3_lane_f16 vld3_lane_f16 |
| #define simde_vld3_lane_f32 vld3_lane_f32 |
| #define simde_vld3_lane_f64 vld3_lane_f64 |
| #define simde_vld3_lane_p16 vld3_lane_p16 |
| #define simde_vld3_lane_p64 vld3_lane_p64 |
| #define simde_vld3_lane_p8 vld3_lane_p8 |
| #define simde_vld3_lane_s16 vld3_lane_s16 |
| #define simde_vld3_lane_s32 vld3_lane_s32 |
| #define simde_vld3_lane_s64 vld3_lane_s64 |
| #define simde_vld3_lane_s8 vld3_lane_s8 |
| #define simde_vld3_lane_u16 vld3_lane_u16 |
| #define simde_vld3_lane_u32 vld3_lane_u32 |
| #define simde_vld3_lane_u64 vld3_lane_u64 |
| #define simde_vld3_lane_u8 vld3_lane_u8 |
| #define simde_vld3_p16 vld3_p16 |
| #define simde_vld3_p64 vld3_p64 |
| #define simde_vld3_p8 vld3_p8 |
| #define simde_vld3_s16 vld3_s16 |
| #define simde_vld3_s32 vld3_s32 |
| #define simde_vld3_s64 vld3_s64 |
| #define simde_vld3_s8 vld3_s8 |
| #define simde_vld3_u16 vld3_u16 |
| #define simde_vld3_u32 vld3_u32 |
| #define simde_vld3_u64 vld3_u64 |
| #define simde_vld3_u8 vld3_u8 |
| #define simde_vld3q_bf16 vld3q_bf16 |
| #define simde_vld3q_dup_bf16 vld3q_dup_bf16 |
| #define simde_vld3q_dup_f16 vld3q_dup_f16 |
| #define simde_vld3q_dup_f32 vld3q_dup_f32 |
| #define simde_vld3q_dup_f64 vld3q_dup_f64 |
| #define simde_vld3q_dup_p16 vld3q_dup_p16 |
| #define simde_vld3q_dup_p64 vld3q_dup_p64 |
| #define simde_vld3q_dup_p8 vld3q_dup_p8 |
| #define simde_vld3q_dup_s16 vld3q_dup_s16 |
| #define simde_vld3q_dup_s32 vld3q_dup_s32 |
| #define simde_vld3q_dup_s64 vld3q_dup_s64 |
| #define simde_vld3q_dup_s8 vld3q_dup_s8 |
| #define simde_vld3q_dup_u16 vld3q_dup_u16 |
| #define simde_vld3q_dup_u32 vld3q_dup_u32 |
| #define simde_vld3q_dup_u64 vld3q_dup_u64 |
| #define simde_vld3q_dup_u8 vld3q_dup_u8 |
| #define simde_vld3q_f16 vld3q_f16 |
| #define simde_vld3q_f32 vld3q_f32 |
| #define simde_vld3q_f64 vld3q_f64 |
| #define simde_vld3q_lane_bf16 vld3q_lane_bf16 |
| #define simde_vld3q_lane_f16 vld3q_lane_f16 |
| #define simde_vld3q_lane_f32 vld3q_lane_f32 |
| #define simde_vld3q_lane_f64 vld3q_lane_f64 |
| #define simde_vld3q_lane_p16 vld3q_lane_p16 |
| #define simde_vld3q_lane_p64 vld3q_lane_p64 |
| #define simde_vld3q_lane_p8 vld3q_lane_p8 |
| #define simde_vld3q_lane_s16 vld3q_lane_s16 |
| #define simde_vld3q_lane_s32 vld3q_lane_s32 |
| #define simde_vld3q_lane_s64 vld3q_lane_s64 |
| #define simde_vld3q_lane_s8 vld3q_lane_s8 |
| #define simde_vld3q_lane_u16 vld3q_lane_u16 |
| #define simde_vld3q_lane_u32 vld3q_lane_u32 |
| #define simde_vld3q_lane_u64 vld3q_lane_u64 |
| #define simde_vld3q_lane_u8 vld3q_lane_u8 |
| #define simde_vld3q_p16 vld3q_p16 |
| #define simde_vld3q_p64 vld3q_p64 |
| #define simde_vld3q_p8 vld3q_p8 |
| #define simde_vld3q_s16 vld3q_s16 |
| #define simde_vld3q_s32 vld3q_s32 |
| #define simde_vld3q_s64 vld3q_s64 |
| #define simde_vld3q_s8 vld3q_s8 |
| #define simde_vld3q_u16 vld3q_u16 |
| #define simde_vld3q_u32 vld3q_u32 |
| #define simde_vld3q_u64 vld3q_u64 |
| #define simde_vld3q_u8 vld3q_u8 |
| #define simde_vld4_bf16 vld4_bf16 |
| #define simde_vld4_dup_bf16 vld4_dup_bf16 |
| #define simde_vld4_dup_f16 vld4_dup_f16 |
| #define simde_vld4_dup_f32 vld4_dup_f32 |
| #define simde_vld4_dup_f64 vld4_dup_f64 |
| #define simde_vld4_dup_p16 vld4_dup_p16 |
| #define simde_vld4_dup_p64 vld4_dup_p64 |
| #define simde_vld4_dup_p8 vld4_dup_p8 |
| #define simde_vld4_dup_s16 vld4_dup_s16 |
| #define simde_vld4_dup_s32 vld4_dup_s32 |
| #define simde_vld4_dup_s64 vld4_dup_s64 |
| #define simde_vld4_dup_s8 vld4_dup_s8 |
| #define simde_vld4_dup_u16 vld4_dup_u16 |
| #define simde_vld4_dup_u32 vld4_dup_u32 |
| #define simde_vld4_dup_u64 vld4_dup_u64 |
| #define simde_vld4_dup_u8 vld4_dup_u8 |
| #define simde_vld4_f16 vld4_f16 |
| #define simde_vld4_f32 vld4_f32 |
| #define simde_vld4_f64 vld4_f64 |
| #define simde_vld4_lane_bf16 vld4_lane_bf16 |
| #define simde_vld4_lane_f16 vld4_lane_f16 |
| #define simde_vld4_lane_f32 vld4_lane_f32 |
| #define simde_vld4_lane_f64 vld4_lane_f64 |
| #define simde_vld4_lane_p16 vld4_lane_p16 |
| #define simde_vld4_lane_p64 vld4_lane_p64 |
| #define simde_vld4_lane_p8 vld4_lane_p8 |
| #define simde_vld4_lane_s16 vld4_lane_s16 |
| #define simde_vld4_lane_s32 vld4_lane_s32 |
| #define simde_vld4_lane_s64 vld4_lane_s64 |
| #define simde_vld4_lane_s8 vld4_lane_s8 |
| #define simde_vld4_lane_u16 vld4_lane_u16 |
| #define simde_vld4_lane_u32 vld4_lane_u32 |
| #define simde_vld4_lane_u64 vld4_lane_u64 |
| #define simde_vld4_lane_u8 vld4_lane_u8 |
| #define simde_vld4_p16 vld4_p16 |
| #define simde_vld4_p64 vld4_p64 |
| #define simde_vld4_p8 vld4_p8 |
| #define simde_vld4_s16 vld4_s16 |
| #define simde_vld4_s32 vld4_s32 |
| #define simde_vld4_s64 vld4_s64 |
| #define simde_vld4_s8 vld4_s8 |
| #define simde_vld4_u16 vld4_u16 |
| #define simde_vld4_u32 vld4_u32 |
| #define simde_vld4_u64 vld4_u64 |
| #define simde_vld4_u8 vld4_u8 |
| #define simde_vld4q_bf16 vld4q_bf16 |
| #define simde_vld4q_dup_bf16 vld4q_dup_bf16 |
| #define simde_vld4q_dup_f16 vld4q_dup_f16 |
| #define simde_vld4q_dup_f32 vld4q_dup_f32 |
| #define simde_vld4q_dup_f64 vld4q_dup_f64 |
| #define simde_vld4q_dup_p16 vld4q_dup_p16 |
| #define simde_vld4q_dup_p64 vld4q_dup_p64 |
| #define simde_vld4q_dup_p8 vld4q_dup_p8 |
| #define simde_vld4q_dup_s16 vld4q_dup_s16 |
| #define simde_vld4q_dup_s32 vld4q_dup_s32 |
| #define simde_vld4q_dup_s64 vld4q_dup_s64 |
| #define simde_vld4q_dup_s8 vld4q_dup_s8 |
| #define simde_vld4q_dup_u16 vld4q_dup_u16 |
| #define simde_vld4q_dup_u32 vld4q_dup_u32 |
| #define simde_vld4q_dup_u64 vld4q_dup_u64 |
| #define simde_vld4q_dup_u8 vld4q_dup_u8 |
| #define simde_vld4q_f16 vld4q_f16 |
| #define simde_vld4q_f32 vld4q_f32 |
| #define simde_vld4q_f64 vld4q_f64 |
| #define simde_vld4q_lane_bf16 vld4q_lane_bf16 |
| #define simde_vld4q_lane_f16 vld4q_lane_f16 |
| #define simde_vld4q_lane_f32 vld4q_lane_f32 |
| #define simde_vld4q_lane_f64 vld4q_lane_f64 |
| #define simde_vld4q_lane_p16 vld4q_lane_p16 |
| #define simde_vld4q_lane_p64 vld4q_lane_p64 |
| #define simde_vld4q_lane_p8 vld4q_lane_p8 |
| #define simde_vld4q_lane_s16 vld4q_lane_s16 |
| #define simde_vld4q_lane_s32 vld4q_lane_s32 |
| #define simde_vld4q_lane_s64 vld4q_lane_s64 |
| #define simde_vld4q_lane_s8 vld4q_lane_s8 |
| #define simde_vld4q_lane_u16 vld4q_lane_u16 |
| #define simde_vld4q_lane_u32 vld4q_lane_u32 |
| #define simde_vld4q_lane_u64 vld4q_lane_u64 |
| #define simde_vld4q_lane_u8 vld4q_lane_u8 |
| #define simde_vld4q_p16 vld4q_p16 |
| #define simde_vld4q_p64 vld4q_p64 |
| #define simde_vld4q_p8 vld4q_p8 |
| #define simde_vld4q_s16 vld4q_s16 |
| #define simde_vld4q_s32 vld4q_s32 |
| #define simde_vld4q_s64 vld4q_s64 |
| #define simde_vld4q_s8 vld4q_s8 |
| #define simde_vld4q_u16 vld4q_u16 |
| #define simde_vld4q_u32 vld4q_u32 |
| #define simde_vld4q_u64 vld4q_u64 |
| #define simde_vld4q_u8 vld4q_u8 |
| #define simde_vldrq_p128 vldrq_p128 |
| #define simde_vmax_f16 vmax_f16 |
| #define simde_vmax_f32 vmax_f32 |
| #define simde_vmax_f64 vmax_f64 |
| #define simde_vmax_s16 vmax_s16 |
| #define simde_vmax_s32 vmax_s32 |
| #define simde_vmax_s8 vmax_s8 |
| #define simde_vmax_u16 vmax_u16 |
| #define simde_vmax_u32 vmax_u32 |
| #define simde_vmax_u8 vmax_u8 |
| #define simde_vmaxnm_f16 vmaxnm_f16 |
| #define simde_vmaxnm_f32 vmaxnm_f32 |
| #define simde_vmaxnm_f64 vmaxnm_f64 |
| #define simde_vmaxnmq_f16 vmaxnmq_f16 |
| #define simde_vmaxnmq_f32 vmaxnmq_f32 |
| #define simde_vmaxnmq_f64 vmaxnmq_f64 |
| #define simde_vmaxnmv_f16 vmaxnmv_f16 |
| #define simde_vmaxnmv_f32 vmaxnmv_f32 |
| #define simde_vmaxnmvq_f16 vmaxnmvq_f16 |
| #define simde_vmaxnmvq_f32 vmaxnmvq_f32 |
| #define simde_vmaxnmvq_f64 vmaxnmvq_f64 |
| #define simde_vmaxq_f16 vmaxq_f16 |
| #define simde_vmaxq_f32 vmaxq_f32 |
| #define simde_vmaxq_f64 vmaxq_f64 |
| #define simde_vmaxq_s16 vmaxq_s16 |
| #define simde_vmaxq_s32 vmaxq_s32 |
| #define simde_vmaxq_s8 vmaxq_s8 |
| #define simde_vmaxq_u16 vmaxq_u16 |
| #define simde_vmaxq_u32 vmaxq_u32 |
| #define simde_vmaxq_u8 vmaxq_u8 |
| #define simde_vmaxv_f16 vmaxv_f16 |
| #define simde_vmaxv_f32 vmaxv_f32 |
| #define simde_vmaxv_s16 vmaxv_s16 |
| #define simde_vmaxv_s32 vmaxv_s32 |
| #define simde_vmaxv_s8 vmaxv_s8 |
| #define simde_vmaxv_u16 vmaxv_u16 |
| #define simde_vmaxv_u32 vmaxv_u32 |
| #define simde_vmaxv_u8 vmaxv_u8 |
| #define simde_vmaxvq_f16 vmaxvq_f16 |
| #define simde_vmaxvq_f32 vmaxvq_f32 |
| #define simde_vmaxvq_f64 vmaxvq_f64 |
| #define simde_vmaxvq_s16 vmaxvq_s16 |
| #define simde_vmaxvq_s32 vmaxvq_s32 |
| #define simde_vmaxvq_s8 vmaxvq_s8 |
| #define simde_vmaxvq_u16 vmaxvq_u16 |
| #define simde_vmaxvq_u32 vmaxvq_u32 |
| #define simde_vmaxvq_u8 vmaxvq_u8 |
| #define simde_vmin_f16 vmin_f16 |
| #define simde_vmin_f32 vmin_f32 |
| #define simde_vmin_f64 vmin_f64 |
| #define simde_vmin_s16 vmin_s16 |
| #define simde_vmin_s32 vmin_s32 |
| #define simde_vmin_s8 vmin_s8 |
| #define simde_vmin_u16 vmin_u16 |
| #define simde_vmin_u32 vmin_u32 |
| #define simde_vmin_u8 vmin_u8 |
| #define simde_vminnm_f16 vminnm_f16 |
| #define simde_vminnm_f32 vminnm_f32 |
| #define simde_vminnm_f64 vminnm_f64 |
| #define simde_vminnmq_f16 vminnmq_f16 |
| #define simde_vminnmq_f32 vminnmq_f32 |
| #define simde_vminnmq_f64 vminnmq_f64 |
| #define simde_vminnmv_f16 vminnmv_f16 |
| #define simde_vminnmv_f32 vminnmv_f32 |
| #define simde_vminnmvq_f16 vminnmvq_f16 |
| #define simde_vminnmvq_f32 vminnmvq_f32 |
| #define simde_vminnmvq_f64 vminnmvq_f64 |
| #define simde_vminq_f16 vminq_f16 |
| #define simde_vminq_f32 vminq_f32 |
| #define simde_vminq_f64 vminq_f64 |
| #define simde_vminq_s16 vminq_s16 |
| #define simde_vminq_s32 vminq_s32 |
| #define simde_vminq_s8 vminq_s8 |
| #define simde_vminq_u16 vminq_u16 |
| #define simde_vminq_u32 vminq_u32 |
| #define simde_vminq_u8 vminq_u8 |
| #define simde_vminv_f16 vminv_f16 |
| #define simde_vminv_f32 vminv_f32 |
| #define simde_vminv_s16 vminv_s16 |
| #define simde_vminv_s32 vminv_s32 |
| #define simde_vminv_s8 vminv_s8 |
| #define simde_vminv_u16 vminv_u16 |
| #define simde_vminv_u32 vminv_u32 |
| #define simde_vminv_u8 vminv_u8 |
| #define simde_vminvq_f16 vminvq_f16 |
| #define simde_vminvq_f32 vminvq_f32 |
| #define simde_vminvq_f64 vminvq_f64 |
| #define simde_vminvq_s16 vminvq_s16 |
| #define simde_vminvq_s32 vminvq_s32 |
| #define simde_vminvq_s8 vminvq_s8 |
| #define simde_vminvq_u16 vminvq_u16 |
| #define simde_vminvq_u32 vminvq_u32 |
| #define simde_vminvq_u8 vminvq_u8 |
| #define simde_vmla_f32 vmla_f32 |
| #define simde_vmla_f64 vmla_f64 |
| #define simde_vmla_lane_f32 vmla_lane_f32 |
| #define simde_vmla_lane_s16 vmla_lane_s16 |
| #define simde_vmla_lane_s32 vmla_lane_s32 |
| #define simde_vmla_lane_u16 vmla_lane_u16 |
| #define simde_vmla_lane_u32 vmla_lane_u32 |
| #define simde_vmla_laneq_f32 vmla_laneq_f32 |
| #define simde_vmla_laneq_s16 vmla_laneq_s16 |
| #define simde_vmla_laneq_s32 vmla_laneq_s32 |
| #define simde_vmla_laneq_u16 vmla_laneq_u16 |
| #define simde_vmla_laneq_u32 vmla_laneq_u32 |
| #define simde_vmla_n_f32 vmla_n_f32 |
| #define simde_vmla_n_s16 vmla_n_s16 |
| #define simde_vmla_n_s32 vmla_n_s32 |
| #define simde_vmla_n_u16 vmla_n_u16 |
| #define simde_vmla_n_u32 vmla_n_u32 |
| #define simde_vmla_s16 vmla_s16 |
| #define simde_vmla_s32 vmla_s32 |
| #define simde_vmla_s8 vmla_s8 |
| #define simde_vmla_u16 vmla_u16 |
| #define simde_vmla_u32 vmla_u32 |
| #define simde_vmla_u8 vmla_u8 |
| #define simde_vmlal_high_lane_s16 vmlal_high_lane_s16 |
| #define simde_vmlal_high_lane_s32 vmlal_high_lane_s32 |
| #define simde_vmlal_high_lane_u16 vmlal_high_lane_u16 |
| #define simde_vmlal_high_lane_u32 vmlal_high_lane_u32 |
| #define simde_vmlal_high_laneq_s16 vmlal_high_laneq_s16 |
| #define simde_vmlal_high_laneq_s32 vmlal_high_laneq_s32 |
| #define simde_vmlal_high_laneq_u16 vmlal_high_laneq_u16 |
| #define simde_vmlal_high_laneq_u32 vmlal_high_laneq_u32 |
| #define simde_vmlal_high_n_s16 vmlal_high_n_s16 |
| #define simde_vmlal_high_n_s32 vmlal_high_n_s32 |
| #define simde_vmlal_high_n_u16 vmlal_high_n_u16 |
| #define simde_vmlal_high_n_u32 vmlal_high_n_u32 |
| #define simde_vmlal_high_s16 vmlal_high_s16 |
| #define simde_vmlal_high_s32 vmlal_high_s32 |
| #define simde_vmlal_high_s8 vmlal_high_s8 |
| #define simde_vmlal_high_u16 vmlal_high_u16 |
| #define simde_vmlal_high_u32 vmlal_high_u32 |
| #define simde_vmlal_high_u8 vmlal_high_u8 |
| #define simde_vmlal_lane_s16 vmlal_lane_s16 |
| #define simde_vmlal_lane_s32 vmlal_lane_s32 |
| #define simde_vmlal_lane_u16 vmlal_lane_u16 |
| #define simde_vmlal_lane_u32 vmlal_lane_u32 |
| #define simde_vmlal_laneq_s16 vmlal_laneq_s16 |
| #define simde_vmlal_laneq_s32 vmlal_laneq_s32 |
| #define simde_vmlal_laneq_u16 vmlal_laneq_u16 |
| #define simde_vmlal_laneq_u32 vmlal_laneq_u32 |
| #define simde_vmlal_n_s16 vmlal_n_s16 |
| #define simde_vmlal_n_s32 vmlal_n_s32 |
| #define simde_vmlal_n_u16 vmlal_n_u16 |
| #define simde_vmlal_n_u32 vmlal_n_u32 |
| #define simde_vmlal_s16 vmlal_s16 |
| #define simde_vmlal_s32 vmlal_s32 |
| #define simde_vmlal_s8 vmlal_s8 |
| #define simde_vmlal_u16 vmlal_u16 |
| #define simde_vmlal_u32 vmlal_u32 |
| #define simde_vmlal_u8 vmlal_u8 |
| #define simde_vmlaq_f32 vmlaq_f32 |
| #define simde_vmlaq_f64 vmlaq_f64 |
| #define simde_vmlaq_lane_f32 vmlaq_lane_f32 |
| #define simde_vmlaq_lane_s16 vmlaq_lane_s16 |
| #define simde_vmlaq_lane_s32 vmlaq_lane_s32 |
| #define simde_vmlaq_lane_u16 vmlaq_lane_u16 |
| #define simde_vmlaq_lane_u32 vmlaq_lane_u32 |
| #define simde_vmlaq_laneq_f32 vmlaq_laneq_f32 |
| #define simde_vmlaq_laneq_s16 vmlaq_laneq_s16 |
| #define simde_vmlaq_laneq_s32 vmlaq_laneq_s32 |
| #define simde_vmlaq_laneq_u16 vmlaq_laneq_u16 |
| #define simde_vmlaq_laneq_u32 vmlaq_laneq_u32 |
| #define simde_vmlaq_n_f32 vmlaq_n_f32 |
| #define simde_vmlaq_n_s16 vmlaq_n_s16 |
| #define simde_vmlaq_n_s32 vmlaq_n_s32 |
| #define simde_vmlaq_n_u16 vmlaq_n_u16 |
| #define simde_vmlaq_n_u32 vmlaq_n_u32 |
| #define simde_vmlaq_s16 vmlaq_s16 |
| #define simde_vmlaq_s32 vmlaq_s32 |
| #define simde_vmlaq_s8 vmlaq_s8 |
| #define simde_vmlaq_u16 vmlaq_u16 |
| #define simde_vmlaq_u32 vmlaq_u32 |
| #define simde_vmlaq_u8 vmlaq_u8 |
| #define simde_vmls_f32 vmls_f32 |
| #define simde_vmls_f64 vmls_f64 |
| #define simde_vmls_lane_f32 vmls_lane_f32 |
| #define simde_vmls_lane_s16 vmls_lane_s16 |
| #define simde_vmls_lane_s32 vmls_lane_s32 |
| #define simde_vmls_lane_u16 vmls_lane_u16 |
| #define simde_vmls_lane_u32 vmls_lane_u32 |
| #define simde_vmls_laneq_f32 vmls_laneq_f32 |
| #define simde_vmls_laneq_s16 vmls_laneq_s16 |
| #define simde_vmls_laneq_s32 vmls_laneq_s32 |
| #define simde_vmls_laneq_u16 vmls_laneq_u16 |
| #define simde_vmls_laneq_u32 vmls_laneq_u32 |
| #define simde_vmls_n_f32 vmls_n_f32 |
| #define simde_vmls_n_s16 vmls_n_s16 |
| #define simde_vmls_n_s32 vmls_n_s32 |
| #define simde_vmls_n_u16 vmls_n_u16 |
| #define simde_vmls_n_u32 vmls_n_u32 |
| #define simde_vmls_s16 vmls_s16 |
| #define simde_vmls_s32 vmls_s32 |
| #define simde_vmls_s8 vmls_s8 |
| #define simde_vmls_u16 vmls_u16 |
| #define simde_vmls_u32 vmls_u32 |
| #define simde_vmls_u8 vmls_u8 |
| #define simde_vmlsl_high_lane_s16 vmlsl_high_lane_s16 |
| #define simde_vmlsl_high_lane_s32 vmlsl_high_lane_s32 |
| #define simde_vmlsl_high_lane_u16 vmlsl_high_lane_u16 |
| #define simde_vmlsl_high_lane_u32 vmlsl_high_lane_u32 |
| #define simde_vmlsl_high_laneq_s16 vmlsl_high_laneq_s16 |
| #define simde_vmlsl_high_laneq_s32 vmlsl_high_laneq_s32 |
| #define simde_vmlsl_high_laneq_u16 vmlsl_high_laneq_u16 |
| #define simde_vmlsl_high_laneq_u32 vmlsl_high_laneq_u32 |
| #define simde_vmlsl_high_n_s16 vmlsl_high_n_s16 |
| #define simde_vmlsl_high_n_s32 vmlsl_high_n_s32 |
| #define simde_vmlsl_high_n_u16 vmlsl_high_n_u16 |
| #define simde_vmlsl_high_n_u32 vmlsl_high_n_u32 |
| #define simde_vmlsl_high_s16 vmlsl_high_s16 |
| #define simde_vmlsl_high_s32 vmlsl_high_s32 |
| #define simde_vmlsl_high_s8 vmlsl_high_s8 |
| #define simde_vmlsl_high_u16 vmlsl_high_u16 |
| #define simde_vmlsl_high_u32 vmlsl_high_u32 |
| #define simde_vmlsl_high_u8 vmlsl_high_u8 |
| #define simde_vmlsl_lane_s16 vmlsl_lane_s16 |
| #define simde_vmlsl_lane_s32 vmlsl_lane_s32 |
| #define simde_vmlsl_lane_u16 vmlsl_lane_u16 |
| #define simde_vmlsl_lane_u32 vmlsl_lane_u32 |
| #define simde_vmlsl_laneq_s16 vmlsl_laneq_s16 |
| #define simde_vmlsl_laneq_s32 vmlsl_laneq_s32 |
| #define simde_vmlsl_laneq_u16 vmlsl_laneq_u16 |
| #define simde_vmlsl_laneq_u32 vmlsl_laneq_u32 |
| #define simde_vmlsl_n_s16 vmlsl_n_s16 |
| #define simde_vmlsl_n_s32 vmlsl_n_s32 |
| #define simde_vmlsl_n_u16 vmlsl_n_u16 |
| #define simde_vmlsl_n_u32 vmlsl_n_u32 |
| #define simde_vmlsl_s16 vmlsl_s16 |
| #define simde_vmlsl_s32 vmlsl_s32 |
| #define simde_vmlsl_s8 vmlsl_s8 |
| #define simde_vmlsl_u16 vmlsl_u16 |
| #define simde_vmlsl_u32 vmlsl_u32 |
| #define simde_vmlsl_u8 vmlsl_u8 |
| #define simde_vmlsq_f32 vmlsq_f32 |
| #define simde_vmlsq_f64 vmlsq_f64 |
| #define simde_vmlsq_lane_f32 vmlsq_lane_f32 |
| #define simde_vmlsq_lane_s16 vmlsq_lane_s16 |
| #define simde_vmlsq_lane_s32 vmlsq_lane_s32 |
| #define simde_vmlsq_lane_u16 vmlsq_lane_u16 |
| #define simde_vmlsq_lane_u32 vmlsq_lane_u32 |
| #define simde_vmlsq_laneq_f32 vmlsq_laneq_f32 |
| #define simde_vmlsq_laneq_s16 vmlsq_laneq_s16 |
| #define simde_vmlsq_laneq_s32 vmlsq_laneq_s32 |
| #define simde_vmlsq_laneq_u16 vmlsq_laneq_u16 |
| #define simde_vmlsq_laneq_u32 vmlsq_laneq_u32 |
| #define simde_vmlsq_n_f32 vmlsq_n_f32 |
| #define simde_vmlsq_n_s16 vmlsq_n_s16 |
| #define simde_vmlsq_n_s32 vmlsq_n_s32 |
| #define simde_vmlsq_n_u16 vmlsq_n_u16 |
| #define simde_vmlsq_n_u32 vmlsq_n_u32 |
| #define simde_vmlsq_s16 vmlsq_s16 |
| #define simde_vmlsq_s32 vmlsq_s32 |
| #define simde_vmlsq_s8 vmlsq_s8 |
| #define simde_vmlsq_u16 vmlsq_u16 |
| #define simde_vmlsq_u32 vmlsq_u32 |
| #define simde_vmlsq_u8 vmlsq_u8 |
| #define simde_vmmlaq_s32 vmmlaq_s32 |
| #define simde_vmmlaq_u32 vmmlaq_u32 |
| #define simde_vmov_n_f16 vmov_n_f16 |
| #define simde_vmov_n_f32 vmov_n_f32 |
| #define simde_vmov_n_f64 vmov_n_f64 |
| #define simde_vmov_n_p16 vmov_n_p16 |
| #define simde_vmov_n_p8 vmov_n_p8 |
| #define simde_vmov_n_s16 vmov_n_s16 |
| #define simde_vmov_n_s32 vmov_n_s32 |
| #define simde_vmov_n_s64 vmov_n_s64 |
| #define simde_vmov_n_s8 vmov_n_s8 |
| #define simde_vmov_n_u16 vmov_n_u16 |
| #define simde_vmov_n_u32 vmov_n_u32 |
| #define simde_vmov_n_u64 vmov_n_u64 |
| #define simde_vmov_n_u8 vmov_n_u8 |
| #define simde_vmovl_high_s16 vmovl_high_s16 |
| #define simde_vmovl_high_s32 vmovl_high_s32 |
| #define simde_vmovl_high_s8 vmovl_high_s8 |
| #define simde_vmovl_high_u16 vmovl_high_u16 |
| #define simde_vmovl_high_u32 vmovl_high_u32 |
| #define simde_vmovl_high_u8 vmovl_high_u8 |
| #define simde_vmovl_s16 vmovl_s16 |
| #define simde_vmovl_s32 vmovl_s32 |
| #define simde_vmovl_s8 vmovl_s8 |
| #define simde_vmovl_u16 vmovl_u16 |
| #define simde_vmovl_u32 vmovl_u32 |
| #define simde_vmovl_u8 vmovl_u8 |
| #define simde_vmovn_high_s16 vmovn_high_s16 |
| #define simde_vmovn_high_s32 vmovn_high_s32 |
| #define simde_vmovn_high_s64 vmovn_high_s64 |
| #define simde_vmovn_high_u16 vmovn_high_u16 |
| #define simde_vmovn_high_u32 vmovn_high_u32 |
| #define simde_vmovn_high_u64 vmovn_high_u64 |
| #define simde_vmovn_s16 vmovn_s16 |
| #define simde_vmovn_s32 vmovn_s32 |
| #define simde_vmovn_s64 vmovn_s64 |
| #define simde_vmovn_u16 vmovn_u16 |
| #define simde_vmovn_u32 vmovn_u32 |
| #define simde_vmovn_u64 vmovn_u64 |
| #define simde_vmovq_n_f16 vmovq_n_f16 |
| #define simde_vmovq_n_f32 vmovq_n_f32 |
| #define simde_vmovq_n_f64 vmovq_n_f64 |
| #define simde_vmovq_n_p16 vmovq_n_p16 |
| #define simde_vmovq_n_p8 vmovq_n_p8 |
| #define simde_vmovq_n_s16 vmovq_n_s16 |
| #define simde_vmovq_n_s32 vmovq_n_s32 |
| #define simde_vmovq_n_s64 vmovq_n_s64 |
| #define simde_vmovq_n_s8 vmovq_n_s8 |
| #define simde_vmovq_n_u16 vmovq_n_u16 |
| #define simde_vmovq_n_u32 vmovq_n_u32 |
| #define simde_vmovq_n_u64 vmovq_n_u64 |
| #define simde_vmovq_n_u8 vmovq_n_u8 |
| #define simde_vmul_f16 vmul_f16 |
| #define simde_vmul_f32 vmul_f32 |
| #define simde_vmul_f64 vmul_f64 |
| #define simde_vmul_lane_f16 vmul_lane_f16 |
| #define simde_vmul_lane_f32 vmul_lane_f32 |
| #define simde_vmul_lane_f64 vmul_lane_f64 |
| #define simde_vmul_lane_s16 vmul_lane_s16 |
| #define simde_vmul_lane_s32 vmul_lane_s32 |
| #define simde_vmul_lane_u16 vmul_lane_u16 |
| #define simde_vmul_lane_u32 vmul_lane_u32 |
| #define simde_vmul_laneq_f16 vmul_laneq_f16 |
| #define simde_vmul_laneq_f32 vmul_laneq_f32 |
| #define simde_vmul_laneq_f64 vmul_laneq_f64 |
| #define simde_vmul_laneq_s16 vmul_laneq_s16 |
| #define simde_vmul_laneq_s32 vmul_laneq_s32 |
| #define simde_vmul_laneq_u16 vmul_laneq_u16 |
| #define simde_vmul_laneq_u32 vmul_laneq_u32 |
| #define simde_vmul_n_f16 vmul_n_f16 |
| #define simde_vmul_n_f32 vmul_n_f32 |
| #define simde_vmul_n_f64 vmul_n_f64 |
| #define simde_vmul_n_s16 vmul_n_s16 |
| #define simde_vmul_n_s32 vmul_n_s32 |
| #define simde_vmul_n_u16 vmul_n_u16 |
| #define simde_vmul_n_u32 vmul_n_u32 |
| #define simde_vmul_p8 vmul_p8 |
| #define simde_vmul_s16 vmul_s16 |
| #define simde_vmul_s32 vmul_s32 |
| #define simde_vmul_s8 vmul_s8 |
| #define simde_vmul_u16 vmul_u16 |
| #define simde_vmul_u32 vmul_u32 |
| #define simde_vmul_u8 vmul_u8 |
| #define simde_vmuld_lane_f64 vmuld_lane_f64 |
| #define simde_vmuld_laneq_f64 vmuld_laneq_f64 |
| #define simde_vmulh_lane_f16 vmulh_lane_f16 |
| #define simde_vmulh_laneq_f16 vmulh_laneq_f16 |
| #define simde_vmull_high_lane_s16 vmull_high_lane_s16 |
| #define simde_vmull_high_lane_s32 vmull_high_lane_s32 |
| #define simde_vmull_high_lane_u16 vmull_high_lane_u16 |
| #define simde_vmull_high_lane_u32 vmull_high_lane_u32 |
| #define simde_vmull_high_laneq_s16 vmull_high_laneq_s16 |
| #define simde_vmull_high_laneq_s32 vmull_high_laneq_s32 |
| #define simde_vmull_high_laneq_u16 vmull_high_laneq_u16 |
| #define simde_vmull_high_laneq_u32 vmull_high_laneq_u32 |
| #define simde_vmull_high_n_s16 vmull_high_n_s16 |
| #define simde_vmull_high_n_s32 vmull_high_n_s32 |
| #define simde_vmull_high_n_u16 vmull_high_n_u16 |
| #define simde_vmull_high_n_u32 vmull_high_n_u32 |
| #define simde_vmull_high_p64 vmull_high_p64 |
| #define simde_vmull_high_p8 vmull_high_p8 |
| #define simde_vmull_high_s16 vmull_high_s16 |
| #define simde_vmull_high_s32 vmull_high_s32 |
| #define simde_vmull_high_s8 vmull_high_s8 |
| #define simde_vmull_high_u16 vmull_high_u16 |
| #define simde_vmull_high_u32 vmull_high_u32 |
| #define simde_vmull_high_u8 vmull_high_u8 |
| #define simde_vmull_lane_s16 vmull_lane_s16 |
| #define simde_vmull_lane_s32 vmull_lane_s32 |
| #define simde_vmull_lane_u16 vmull_lane_u16 |
| #define simde_vmull_lane_u32 vmull_lane_u32 |
| #define simde_vmull_laneq_s16 vmull_laneq_s16 |
| #define simde_vmull_laneq_s32 vmull_laneq_s32 |
| #define simde_vmull_laneq_u16 vmull_laneq_u16 |
| #define simde_vmull_laneq_u32 vmull_laneq_u32 |
| #define simde_vmull_n_s16 vmull_n_s16 |
| #define simde_vmull_n_s32 vmull_n_s32 |
| #define simde_vmull_n_u16 vmull_n_u16 |
| #define simde_vmull_n_u32 vmull_n_u32 |
| #define simde_vmull_p64 vmull_p64 |
| #define simde_vmull_p8 vmull_p8 |
| #define simde_vmull_s16 vmull_s16 |
| #define simde_vmull_s32 vmull_s32 |
| #define simde_vmull_s8 vmull_s8 |
| #define simde_vmull_u16 vmull_u16 |
| #define simde_vmull_u32 vmull_u32 |
| #define simde_vmull_u8 vmull_u8 |
| #define simde_vmulq_f16 vmulq_f16 |
| #define simde_vmulq_f32 vmulq_f32 |
| #define simde_vmulq_f64 vmulq_f64 |
| #define simde_vmulq_lane_f16 vmulq_lane_f16 |
| #define simde_vmulq_lane_f32 vmulq_lane_f32 |
| #define simde_vmulq_lane_f64 vmulq_lane_f64 |
| #define simde_vmulq_lane_s16 vmulq_lane_s16 |
| #define simde_vmulq_lane_s32 vmulq_lane_s32 |
| #define simde_vmulq_lane_u16 vmulq_lane_u16 |
| #define simde_vmulq_lane_u32 vmulq_lane_u32 |
| #define simde_vmulq_laneq_f16 vmulq_laneq_f16 |
| #define simde_vmulq_laneq_f32 vmulq_laneq_f32 |
| #define simde_vmulq_laneq_f64 vmulq_laneq_f64 |
| #define simde_vmulq_laneq_s16 vmulq_laneq_s16 |
| #define simde_vmulq_laneq_s32 vmulq_laneq_s32 |
| #define simde_vmulq_laneq_u16 vmulq_laneq_u16 |
| #define simde_vmulq_laneq_u32 vmulq_laneq_u32 |
| #define simde_vmulq_n_f16 vmulq_n_f16 |
| #define simde_vmulq_n_f32 vmulq_n_f32 |
| #define simde_vmulq_n_f64 vmulq_n_f64 |
| #define simde_vmulq_n_s16 vmulq_n_s16 |
| #define simde_vmulq_n_s32 vmulq_n_s32 |
| #define simde_vmulq_n_u16 vmulq_n_u16 |
| #define simde_vmulq_n_u32 vmulq_n_u32 |
| #define simde_vmulq_p8 vmulq_p8 |
| #define simde_vmulq_s16 vmulq_s16 |
| #define simde_vmulq_s32 vmulq_s32 |
| #define simde_vmulq_s8 vmulq_s8 |
| #define simde_vmulq_u16 vmulq_u16 |
| #define simde_vmulq_u32 vmulq_u32 |
| #define simde_vmulq_u8 vmulq_u8 |
| #define simde_vmuls_lane_f32 vmuls_lane_f32 |
| #define simde_vmuls_laneq_f32 vmuls_laneq_f32 |
| #define simde_vmulx_f16 vmulx_f16 |
| #define simde_vmulx_f32 vmulx_f32 |
| #define simde_vmulx_f64 vmulx_f64 |
| #define simde_vmulx_lane_f16 vmulx_lane_f16 |
| #define simde_vmulx_lane_f32 vmulx_lane_f32 |
| #define simde_vmulx_lane_f64 vmulx_lane_f64 |
| #define simde_vmulx_laneq_f16 vmulx_laneq_f16 |
| #define simde_vmulx_laneq_f32 vmulx_laneq_f32 |
| #define simde_vmulx_laneq_f64 vmulx_laneq_f64 |
| #define simde_vmulx_n_f16 vmulx_n_f16 |
| #define simde_vmulxd_f64 vmulxd_f64 |
| #define simde_vmulxd_lane_f64 vmulxd_lane_f64 |
| #define simde_vmulxd_laneq_f64 vmulxd_laneq_f64 |
| #define simde_vmulxh_lane_f16 vmulxh_lane_f16 |
| #define simde_vmulxh_laneq_f16 vmulxh_laneq_f16 |
| #define simde_vmulxq_f16 vmulxq_f16 |
| #define simde_vmulxq_f32 vmulxq_f32 |
| #define simde_vmulxq_f64 vmulxq_f64 |
| #define simde_vmulxq_lane_f16 vmulxq_lane_f16 |
| #define simde_vmulxq_lane_f32 vmulxq_lane_f32 |
| #define simde_vmulxq_lane_f64 vmulxq_lane_f64 |
| #define simde_vmulxq_laneq_f16 vmulxq_laneq_f16 |
| #define simde_vmulxq_laneq_f32 vmulxq_laneq_f32 |
| #define simde_vmulxq_laneq_f64 vmulxq_laneq_f64 |
| #define simde_vmulxq_n_f16 vmulxq_n_f16 |
| #define simde_vmulxs_f32 vmulxs_f32 |
| #define simde_vmulxs_lane_f32 vmulxs_lane_f32 |
| #define simde_vmulxs_laneq_f32 vmulxs_laneq_f32 |
| #define simde_vmvn_p8 vmvn_p8 |
| #define simde_vmvn_s16 vmvn_s16 |
| #define simde_vmvn_s32 vmvn_s32 |
| #define simde_vmvn_s8 vmvn_s8 |
| #define simde_vmvn_u16 vmvn_u16 |
| #define simde_vmvn_u32 vmvn_u32 |
| #define simde_vmvn_u8 vmvn_u8 |
| #define simde_vmvnq_p8 vmvnq_p8 |
| #define simde_vmvnq_s16 vmvnq_s16 |
| #define simde_vmvnq_s32 vmvnq_s32 |
| #define simde_vmvnq_s8 vmvnq_s8 |
| #define simde_vmvnq_u16 vmvnq_u16 |
| #define simde_vmvnq_u32 vmvnq_u32 |
| #define simde_vmvnq_u8 vmvnq_u8 |
| #define simde_vneg_f16 vneg_f16 |
| #define simde_vneg_f32 vneg_f32 |
| #define simde_vneg_f64 vneg_f64 |
| #define simde_vneg_s16 vneg_s16 |
| #define simde_vneg_s32 vneg_s32 |
| #define simde_vneg_s64 vneg_s64 |
| #define simde_vneg_s8 vneg_s8 |
| #define simde_vnegd_s64 vnegd_s64 |
| #define simde_vnegq_f16 vnegq_f16 |
| #define simde_vnegq_f32 vnegq_f32 |
| #define simde_vnegq_f64 vnegq_f64 |
| #define simde_vnegq_s16 vnegq_s16 |
| #define simde_vnegq_s32 vnegq_s32 |
| #define simde_vnegq_s64 vnegq_s64 |
| #define simde_vnegq_s8 vnegq_s8 |
| #define simde_vorn_s16 vorn_s16 |
| #define simde_vorn_s32 vorn_s32 |
| #define simde_vorn_s64 vorn_s64 |
| #define simde_vorn_s8 vorn_s8 |
| #define simde_vorn_u16 vorn_u16 |
| #define simde_vorn_u32 vorn_u32 |
| #define simde_vorn_u64 vorn_u64 |
| #define simde_vorn_u8 vorn_u8 |
| #define simde_vornq_s16 vornq_s16 |
| #define simde_vornq_s32 vornq_s32 |
| #define simde_vornq_s64 vornq_s64 |
| #define simde_vornq_s8 vornq_s8 |
| #define simde_vornq_u16 vornq_u16 |
| #define simde_vornq_u32 vornq_u32 |
| #define simde_vornq_u64 vornq_u64 |
| #define simde_vornq_u8 vornq_u8 |
| #define simde_vorr_s16 vorr_s16 |
| #define simde_vorr_s32 vorr_s32 |
| #define simde_vorr_s64 vorr_s64 |
| #define simde_vorr_s8 vorr_s8 |
| #define simde_vorr_u16 vorr_u16 |
| #define simde_vorr_u32 vorr_u32 |
| #define simde_vorr_u64 vorr_u64 |
| #define simde_vorr_u8 vorr_u8 |
| #define simde_vorrq_s16 vorrq_s16 |
| #define simde_vorrq_s32 vorrq_s32 |
| #define simde_vorrq_s64 vorrq_s64 |
| #define simde_vorrq_s8 vorrq_s8 |
| #define simde_vorrq_u16 vorrq_u16 |
| #define simde_vorrq_u32 vorrq_u32 |
| #define simde_vorrq_u64 vorrq_u64 |
| #define simde_vorrq_u8 vorrq_u8 |
| #define simde_vpadal_s16 vpadal_s16 |
| #define simde_vpadal_s32 vpadal_s32 |
| #define simde_vpadal_s8 vpadal_s8 |
| #define simde_vpadal_u16 vpadal_u16 |
| #define simde_vpadal_u32 vpadal_u32 |
| #define simde_vpadal_u8 vpadal_u8 |
| #define simde_vpadalq_s16 vpadalq_s16 |
| #define simde_vpadalq_s32 vpadalq_s32 |
| #define simde_vpadalq_s8 vpadalq_s8 |
| #define simde_vpadalq_u16 vpadalq_u16 |
| #define simde_vpadalq_u32 vpadalq_u32 |
| #define simde_vpadalq_u8 vpadalq_u8 |
| #define simde_vpadd_f16 vpadd_f16 |
| #define simde_vpadd_f32 vpadd_f32 |
| #define simde_vpadd_s16 vpadd_s16 |
| #define simde_vpadd_s32 vpadd_s32 |
| #define simde_vpadd_s8 vpadd_s8 |
| #define simde_vpadd_u16 vpadd_u16 |
| #define simde_vpadd_u32 vpadd_u32 |
| #define simde_vpadd_u8 vpadd_u8 |
| #define simde_vpaddd_f64 vpaddd_f64 |
| #define simde_vpaddd_s64 vpaddd_s64 |
| #define simde_vpaddd_u64 vpaddd_u64 |
| #define simde_vpaddl_s16 vpaddl_s16 |
| #define simde_vpaddl_s32 vpaddl_s32 |
| #define simde_vpaddl_s8 vpaddl_s8 |
| #define simde_vpaddl_u16 vpaddl_u16 |
| #define simde_vpaddl_u32 vpaddl_u32 |
| #define simde_vpaddl_u8 vpaddl_u8 |
| #define simde_vpaddlq_s16 vpaddlq_s16 |
| #define simde_vpaddlq_s32 vpaddlq_s32 |
| #define simde_vpaddlq_s8 vpaddlq_s8 |
| #define simde_vpaddlq_u16 vpaddlq_u16 |
| #define simde_vpaddlq_u32 vpaddlq_u32 |
| #define simde_vpaddlq_u8 vpaddlq_u8 |
| #define simde_vpaddq_f16 vpaddq_f16 |
| #define simde_vpaddq_f32 vpaddq_f32 |
| #define simde_vpaddq_f64 vpaddq_f64 |
| #define simde_vpaddq_s16 vpaddq_s16 |
| #define simde_vpaddq_s32 vpaddq_s32 |
| #define simde_vpaddq_s64 vpaddq_s64 |
| #define simde_vpaddq_s8 vpaddq_s8 |
| #define simde_vpaddq_u16 vpaddq_u16 |
| #define simde_vpaddq_u32 vpaddq_u32 |
| #define simde_vpaddq_u64 vpaddq_u64 |
| #define simde_vpaddq_u8 vpaddq_u8 |
| #define simde_vpadds_f32 vpadds_f32 |
| #define simde_vpmax_f16 vpmax_f16 |
| #define simde_vpmax_f32 vpmax_f32 |
| #define simde_vpmax_s16 vpmax_s16 |
| #define simde_vpmax_s32 vpmax_s32 |
| #define simde_vpmax_s8 vpmax_s8 |
| #define simde_vpmax_u16 vpmax_u16 |
| #define simde_vpmax_u32 vpmax_u32 |
| #define simde_vpmax_u8 vpmax_u8 |
| #define simde_vpmaxnm_f16 vpmaxnm_f16 |
| #define simde_vpmaxnm_f32 vpmaxnm_f32 |
| #define simde_vpmaxnmq_f16 vpmaxnmq_f16 |
| #define simde_vpmaxnmq_f32 vpmaxnmq_f32 |
| #define simde_vpmaxnmq_f64 vpmaxnmq_f64 |
| #define simde_vpmaxnmqd_f64 vpmaxnmqd_f64 |
| #define simde_vpmaxnms_f32 vpmaxnms_f32 |
| #define simde_vpmaxq_f16 vpmaxq_f16 |
| #define simde_vpmaxq_f32 vpmaxq_f32 |
| #define simde_vpmaxq_f64 vpmaxq_f64 |
| #define simde_vpmaxq_s16 vpmaxq_s16 |
| #define simde_vpmaxq_s32 vpmaxq_s32 |
| #define simde_vpmaxq_s8 vpmaxq_s8 |
| #define simde_vpmaxq_u16 vpmaxq_u16 |
| #define simde_vpmaxq_u32 vpmaxq_u32 |
| #define simde_vpmaxq_u8 vpmaxq_u8 |
| #define simde_vpmaxqd_f64 vpmaxqd_f64 |
| #define simde_vpmaxs_f32 vpmaxs_f32 |
| #define simde_vpmin_f16 vpmin_f16 |
| #define simde_vpmin_f32 vpmin_f32 |
| #define simde_vpmin_s16 vpmin_s16 |
| #define simde_vpmin_s32 vpmin_s32 |
| #define simde_vpmin_s8 vpmin_s8 |
| #define simde_vpmin_u16 vpmin_u16 |
| #define simde_vpmin_u32 vpmin_u32 |
| #define simde_vpmin_u8 vpmin_u8 |
| #define simde_vpminnm_f16 vpminnm_f16 |
| #define simde_vpminnm_f32 vpminnm_f32 |
| #define simde_vpminnmq_f16 vpminnmq_f16 |
| #define simde_vpminnmq_f32 vpminnmq_f32 |
| #define simde_vpminnmq_f64 vpminnmq_f64 |
| #define simde_vpminnmqd_f64 vpminnmqd_f64 |
| #define simde_vpminnms_f32 vpminnms_f32 |
| #define simde_vpminq_f16 vpminq_f16 |
| #define simde_vpminq_f32 vpminq_f32 |
| #define simde_vpminq_f64 vpminq_f64 |
| #define simde_vpminq_s16 vpminq_s16 |
| #define simde_vpminq_s32 vpminq_s32 |
| #define simde_vpminq_s8 vpminq_s8 |
| #define simde_vpminq_u16 vpminq_u16 |
| #define simde_vpminq_u32 vpminq_u32 |
| #define simde_vpminq_u8 vpminq_u8 |
| #define simde_vpminqd_f64 vpminqd_f64 |
| #define simde_vpmins_f32 vpmins_f32 |
| #define simde_vqabs_s16 vqabs_s16 |
| #define simde_vqabs_s32 vqabs_s32 |
| #define simde_vqabs_s64 vqabs_s64 |
| #define simde_vqabs_s8 vqabs_s8 |
| #define simde_vqabsb_s8 vqabsb_s8 |
| #define simde_vqabsd_s64 vqabsd_s64 |
| #define simde_vqabsh_s16 vqabsh_s16 |
| #define simde_vqabsq_s16 vqabsq_s16 |
| #define simde_vqabsq_s32 vqabsq_s32 |
| #define simde_vqabsq_s64 vqabsq_s64 |
| #define simde_vqabsq_s8 vqabsq_s8 |
| #define simde_vqabss_s32 vqabss_s32 |
| #define simde_vqadd_s16 vqadd_s16 |
| #define simde_vqadd_s32 vqadd_s32 |
| #define simde_vqadd_s64 vqadd_s64 |
| #define simde_vqadd_s8 vqadd_s8 |
| #define simde_vqadd_u16 vqadd_u16 |
| #define simde_vqadd_u32 vqadd_u32 |
| #define simde_vqadd_u64 vqadd_u64 |
| #define simde_vqadd_u8 vqadd_u8 |
| #define simde_vqaddb_s8 vqaddb_s8 |
| #define simde_vqaddb_u8 vqaddb_u8 |
| #define simde_vqaddd_s64 vqaddd_s64 |
| #define simde_vqaddd_u64 vqaddd_u64 |
| #define simde_vqaddh_s16 vqaddh_s16 |
| #define simde_vqaddh_u16 vqaddh_u16 |
| #define simde_vqaddq_s16 vqaddq_s16 |
| #define simde_vqaddq_s32 vqaddq_s32 |
| #define simde_vqaddq_s64 vqaddq_s64 |
| #define simde_vqaddq_s8 vqaddq_s8 |
| #define simde_vqaddq_u16 vqaddq_u16 |
| #define simde_vqaddq_u32 vqaddq_u32 |
| #define simde_vqaddq_u64 vqaddq_u64 |
| #define simde_vqaddq_u8 vqaddq_u8 |
| #define simde_vqadds_s32 vqadds_s32 |
| #define simde_vqadds_u32 vqadds_u32 |
| #define simde_vqdmlal_high_lane_s16 vqdmlal_high_lane_s16 |
| #define simde_vqdmlal_high_lane_s32 vqdmlal_high_lane_s32 |
| #define simde_vqdmlal_high_laneq_s16 vqdmlal_high_laneq_s16 |
| #define simde_vqdmlal_high_laneq_s32 vqdmlal_high_laneq_s32 |
| #define simde_vqdmlal_high_n_s16 vqdmlal_high_n_s16 |
| #define simde_vqdmlal_high_n_s32 vqdmlal_high_n_s32 |
| #define simde_vqdmlal_high_s16 vqdmlal_high_s16 |
| #define simde_vqdmlal_high_s32 vqdmlal_high_s32 |
| #define simde_vqdmlal_lane_s16 vqdmlal_lane_s16 |
| #define simde_vqdmlal_lane_s32 vqdmlal_lane_s32 |
| #define simde_vqdmlal_laneq_s16 vqdmlal_laneq_s16 |
| #define simde_vqdmlal_laneq_s32 vqdmlal_laneq_s32 |
| #define simde_vqdmlal_n_s16 vqdmlal_n_s16 |
| #define simde_vqdmlal_n_s32 vqdmlal_n_s32 |
| #define simde_vqdmlal_s16 vqdmlal_s16 |
| #define simde_vqdmlal_s32 vqdmlal_s32 |
| #define simde_vqdmlalh_lane_s16 vqdmlalh_lane_s16 |
| #define simde_vqdmlalh_laneq_s16 vqdmlalh_laneq_s16 |
| #define simde_vqdmlalh_s16 vqdmlalh_s16 |
| #define simde_vqdmlals_lane_s32 vqdmlals_lane_s32 |
| #define simde_vqdmlals_laneq_s32 vqdmlals_laneq_s32 |
| #define simde_vqdmlals_s32 vqdmlals_s32 |
| #define simde_vqdmlsl_high_lane_s16 vqdmlsl_high_lane_s16 |
| #define simde_vqdmlsl_high_lane_s32 vqdmlsl_high_lane_s32 |
| #define simde_vqdmlsl_high_laneq_s16 vqdmlsl_high_laneq_s16 |
| #define simde_vqdmlsl_high_laneq_s32 vqdmlsl_high_laneq_s32 |
| #define simde_vqdmlsl_high_n_s16 vqdmlsl_high_n_s16 |
| #define simde_vqdmlsl_high_n_s32 vqdmlsl_high_n_s32 |
| #define simde_vqdmlsl_high_s16 vqdmlsl_high_s16 |
| #define simde_vqdmlsl_high_s32 vqdmlsl_high_s32 |
| #define simde_vqdmlsl_lane_s16 vqdmlsl_lane_s16 |
| #define simde_vqdmlsl_lane_s32 vqdmlsl_lane_s32 |
| #define simde_vqdmlsl_laneq_s16 vqdmlsl_laneq_s16 |
| #define simde_vqdmlsl_laneq_s32 vqdmlsl_laneq_s32 |
| #define simde_vqdmlsl_n_s16 vqdmlsl_n_s16 |
| #define simde_vqdmlsl_n_s32 vqdmlsl_n_s32 |
| #define simde_vqdmlsl_s16 vqdmlsl_s16 |
| #define simde_vqdmlsl_s32 vqdmlsl_s32 |
| #define simde_vqdmlslh_lane_s16 vqdmlslh_lane_s16 |
| #define simde_vqdmlslh_laneq_s16 vqdmlslh_laneq_s16 |
| #define simde_vqdmlslh_s16 vqdmlslh_s16 |
| #define simde_vqdmlsls_lane_s32 vqdmlsls_lane_s32 |
| #define simde_vqdmlsls_laneq_s32 vqdmlsls_laneq_s32 |
| #define simde_vqdmlsls_s32 vqdmlsls_s32 |
| #define simde_vqdmulh_lane_s16 vqdmulh_lane_s16 |
| #define simde_vqdmulh_lane_s32 vqdmulh_lane_s32 |
| #define simde_vqdmulh_laneq_s16 vqdmulh_laneq_s16 |
| #define simde_vqdmulh_laneq_s32 vqdmulh_laneq_s32 |
| #define simde_vqdmulh_n_s16 vqdmulh_n_s16 |
| #define simde_vqdmulh_n_s32 vqdmulh_n_s32 |
| #define simde_vqdmulh_s16 vqdmulh_s16 |
| #define simde_vqdmulh_s32 vqdmulh_s32 |
| #define simde_vqdmulhh_lane_s16 vqdmulhh_lane_s16 |
| #define simde_vqdmulhh_laneq_s16 vqdmulhh_laneq_s16 |
| #define simde_vqdmulhh_s16 vqdmulhh_s16 |
| #define simde_vqdmulhq_lane_s16 vqdmulhq_lane_s16 |
| #define simde_vqdmulhq_lane_s32 vqdmulhq_lane_s32 |
| #define simde_vqdmulhq_laneq_s16 vqdmulhq_laneq_s16 |
| #define simde_vqdmulhq_laneq_s32 vqdmulhq_laneq_s32 |
| #define simde_vqdmulhq_n_s16 vqdmulhq_n_s16 |
| #define simde_vqdmulhq_n_s32 vqdmulhq_n_s32 |
| #define simde_vqdmulhq_s16 vqdmulhq_s16 |
| #define simde_vqdmulhq_s32 vqdmulhq_s32 |
| #define simde_vqdmulhs_lane_s32 vqdmulhs_lane_s32 |
| #define simde_vqdmulhs_laneq_s32 vqdmulhs_laneq_s32 |
| #define simde_vqdmulhs_s32 vqdmulhs_s32 |
| #define simde_vqdmull_high_lane_s16 vqdmull_high_lane_s16 |
| #define simde_vqdmull_high_lane_s32 vqdmull_high_lane_s32 |
| #define simde_vqdmull_high_laneq_s16 vqdmull_high_laneq_s16 |
| #define simde_vqdmull_high_laneq_s32 vqdmull_high_laneq_s32 |
| #define simde_vqdmull_high_n_s16 vqdmull_high_n_s16 |
| #define simde_vqdmull_high_n_s32 vqdmull_high_n_s32 |
| #define simde_vqdmull_high_s16 vqdmull_high_s16 |
| #define simde_vqdmull_high_s32 vqdmull_high_s32 |
| #define simde_vqdmull_lane_s16 vqdmull_lane_s16 |
| #define simde_vqdmull_lane_s32 vqdmull_lane_s32 |
| #define simde_vqdmull_laneq_s16 vqdmull_laneq_s16 |
| #define simde_vqdmull_laneq_s32 vqdmull_laneq_s32 |
| #define simde_vqdmull_n_s16 vqdmull_n_s16 |
| #define simde_vqdmull_n_s32 vqdmull_n_s32 |
| #define simde_vqdmull_s16 vqdmull_s16 |
| #define simde_vqdmull_s32 vqdmull_s32 |
| #define simde_vqdmullh_lane_s16 vqdmullh_lane_s16 |
| #define simde_vqdmullh_laneq_s16 vqdmullh_laneq_s16 |
| #define simde_vqdmullh_s16 vqdmullh_s16 |
| #define simde_vqdmulls_lane_s32 vqdmulls_lane_s32 |
| #define simde_vqdmulls_laneq_s32 vqdmulls_laneq_s32 |
| #define simde_vqdmulls_s32 vqdmulls_s32 |
| #define simde_vqmovn_high_s16 vqmovn_high_s16 |
| #define simde_vqmovn_high_s32 vqmovn_high_s32 |
| #define simde_vqmovn_high_s64 vqmovn_high_s64 |
| #define simde_vqmovn_high_u16 vqmovn_high_u16 |
| #define simde_vqmovn_high_u32 vqmovn_high_u32 |
| #define simde_vqmovn_high_u64 vqmovn_high_u64 |
| #define simde_vqmovn_s16 vqmovn_s16 |
| #define simde_vqmovn_s32 vqmovn_s32 |
| #define simde_vqmovn_s64 vqmovn_s64 |
| #define simde_vqmovn_u16 vqmovn_u16 |
| #define simde_vqmovn_u32 vqmovn_u32 |
| #define simde_vqmovn_u64 vqmovn_u64 |
| #define simde_vqmovnd_s64 vqmovnd_s64 |
| #define simde_vqmovnd_u64 vqmovnd_u64 |
| #define simde_vqmovnh_s16 vqmovnh_s16 |
| #define simde_vqmovnh_u16 vqmovnh_u16 |
| #define simde_vqmovns_s32 vqmovns_s32 |
| #define simde_vqmovns_u32 vqmovns_u32 |
| #define simde_vqmovun_high_s16 vqmovun_high_s16 |
| #define simde_vqmovun_high_s32 vqmovun_high_s32 |
| #define simde_vqmovun_high_s64 vqmovun_high_s64 |
| #define simde_vqmovun_s16 vqmovun_s16 |
| #define simde_vqmovun_s32 vqmovun_s32 |
| #define simde_vqmovun_s64 vqmovun_s64 |
| #define simde_vqmovund_s64 vqmovund_s64 |
| #define simde_vqmovunh_s16 vqmovunh_s16 |
| #define simde_vqmovuns_s32 vqmovuns_s32 |
| #define simde_vqneg_s16 vqneg_s16 |
| #define simde_vqneg_s32 vqneg_s32 |
| #define simde_vqneg_s64 vqneg_s64 |
| #define simde_vqneg_s8 vqneg_s8 |
| #define simde_vqnegb_s8 vqnegb_s8 |
| #define simde_vqnegd_s64 vqnegd_s64 |
| #define simde_vqnegh_s16 vqnegh_s16 |
| #define simde_vqnegq_s16 vqnegq_s16 |
| #define simde_vqnegq_s32 vqnegq_s32 |
| #define simde_vqnegq_s64 vqnegq_s64 |
| #define simde_vqnegq_s8 vqnegq_s8 |
| #define simde_vqnegs_s32 vqnegs_s32 |
| #define simde_vqrdmlah_lane_s16 vqrdmlah_lane_s16 |
| #define simde_vqrdmlah_lane_s32 vqrdmlah_lane_s32 |
| #define simde_vqrdmlah_laneq_s16 vqrdmlah_laneq_s16 |
| #define simde_vqrdmlah_laneq_s32 vqrdmlah_laneq_s32 |
| #define simde_vqrdmlah_s16 vqrdmlah_s16 |
| #define simde_vqrdmlah_s32 vqrdmlah_s32 |
| #define simde_vqrdmlahh_lane_s16 vqrdmlahh_lane_s16 |
| #define simde_vqrdmlahh_laneq_s16 vqrdmlahh_laneq_s16 |
| #define simde_vqrdmlahh_s16 vqrdmlahh_s16 |
| #define simde_vqrdmlahq_lane_s16 vqrdmlahq_lane_s16 |
| #define simde_vqrdmlahq_lane_s32 vqrdmlahq_lane_s32 |
| #define simde_vqrdmlahq_laneq_s16 vqrdmlahq_laneq_s16 |
| #define simde_vqrdmlahq_laneq_s32 vqrdmlahq_laneq_s32 |
| #define simde_vqrdmlahq_s16 vqrdmlahq_s16 |
| #define simde_vqrdmlahq_s32 vqrdmlahq_s32 |
| #define simde_vqrdmlahs_lane_s32 vqrdmlahs_lane_s32 |
| #define simde_vqrdmlahs_laneq_s32 vqrdmlahs_laneq_s32 |
| #define simde_vqrdmlahs_s32 vqrdmlahs_s32 |
| #define simde_vqrdmlsh_lane_s16 vqrdmlsh_lane_s16 |
| #define simde_vqrdmlsh_lane_s32 vqrdmlsh_lane_s32 |
| #define simde_vqrdmlsh_laneq_s16 vqrdmlsh_laneq_s16 |
| #define simde_vqrdmlsh_laneq_s32 vqrdmlsh_laneq_s32 |
| #define simde_vqrdmlsh_s16 vqrdmlsh_s16 |
| #define simde_vqrdmlsh_s32 vqrdmlsh_s32 |
| #define simde_vqrdmlshh_lane_s16 vqrdmlshh_lane_s16 |
| #define simde_vqrdmlshh_laneq_s16 vqrdmlshh_laneq_s16 |
| #define simde_vqrdmlshh_s16 vqrdmlshh_s16 |
| #define simde_vqrdmlshq_lane_s16 vqrdmlshq_lane_s16 |
| #define simde_vqrdmlshq_lane_s32 vqrdmlshq_lane_s32 |
| #define simde_vqrdmlshq_laneq_s16 vqrdmlshq_laneq_s16 |
| #define simde_vqrdmlshq_laneq_s32 vqrdmlshq_laneq_s32 |
| #define simde_vqrdmlshq_s16 vqrdmlshq_s16 |
| #define simde_vqrdmlshq_s32 vqrdmlshq_s32 |
| #define simde_vqrdmlshs_lane_s32 vqrdmlshs_lane_s32 |
| #define simde_vqrdmlshs_laneq_s32 vqrdmlshs_laneq_s32 |
| #define simde_vqrdmlshs_s32 vqrdmlshs_s32 |
| #define simde_vqrdmulh_lane_s16 vqrdmulh_lane_s16 |
| #define simde_vqrdmulh_lane_s32 vqrdmulh_lane_s32 |
| #define simde_vqrdmulh_laneq_s16 vqrdmulh_laneq_s16 |
| #define simde_vqrdmulh_laneq_s32 vqrdmulh_laneq_s32 |
| #define simde_vqrdmulh_n_s16 vqrdmulh_n_s16 |
| #define simde_vqrdmulh_n_s32 vqrdmulh_n_s32 |
| #define simde_vqrdmulh_s16 vqrdmulh_s16 |
| #define simde_vqrdmulh_s32 vqrdmulh_s32 |
| #define simde_vqrdmulhh_lane_s16 vqrdmulhh_lane_s16 |
| #define simde_vqrdmulhh_laneq_s16 vqrdmulhh_laneq_s16 |
| #define simde_vqrdmulhh_s16 vqrdmulhh_s16 |
| #define simde_vqrdmulhq_lane_s16 vqrdmulhq_lane_s16 |
| #define simde_vqrdmulhq_lane_s32 vqrdmulhq_lane_s32 |
| #define simde_vqrdmulhq_laneq_s16 vqrdmulhq_laneq_s16 |
| #define simde_vqrdmulhq_laneq_s32 vqrdmulhq_laneq_s32 |
| #define simde_vqrdmulhq_n_s16 vqrdmulhq_n_s16 |
| #define simde_vqrdmulhq_n_s32 vqrdmulhq_n_s32 |
| #define simde_vqrdmulhq_s16 vqrdmulhq_s16 |
| #define simde_vqrdmulhq_s32 vqrdmulhq_s32 |
| #define simde_vqrdmulhs_lane_s32 vqrdmulhs_lane_s32 |
| #define simde_vqrdmulhs_laneq_s32 vqrdmulhs_laneq_s32 |
| #define simde_vqrdmulhs_s32 vqrdmulhs_s32 |
| #define simde_vqrshl_s16 vqrshl_s16 |
| #define simde_vqrshl_s32 vqrshl_s32 |
| #define simde_vqrshl_s64 vqrshl_s64 |
| #define simde_vqrshl_s8 vqrshl_s8 |
| #define simde_vqrshl_u16 vqrshl_u16 |
| #define simde_vqrshl_u32 vqrshl_u32 |
| #define simde_vqrshl_u64 vqrshl_u64 |
| #define simde_vqrshl_u8 vqrshl_u8 |
| #define simde_vqrshlb_s8 vqrshlb_s8 |
| #define simde_vqrshlb_u8 vqrshlb_u8 |
| #define simde_vqrshld_s64 vqrshld_s64 |
| #define simde_vqrshld_u64 vqrshld_u64 |
| #define simde_vqrshlh_s16 vqrshlh_s16 |
| #define simde_vqrshlh_u16 vqrshlh_u16 |
| #define simde_vqrshlq_s16 vqrshlq_s16 |
| #define simde_vqrshlq_s32 vqrshlq_s32 |
| #define simde_vqrshlq_s64 vqrshlq_s64 |
| #define simde_vqrshlq_s8 vqrshlq_s8 |
| #define simde_vqrshlq_u16 vqrshlq_u16 |
| #define simde_vqrshlq_u32 vqrshlq_u32 |
| #define simde_vqrshlq_u64 vqrshlq_u64 |
| #define simde_vqrshlq_u8 vqrshlq_u8 |
| #define simde_vqrshls_s32 vqrshls_s32 |
| #define simde_vqrshls_u32 vqrshls_u32 |
| #define simde_vqrshrn_high_n_s16 vqrshrn_high_n_s16 |
| #define simde_vqrshrn_high_n_s32 vqrshrn_high_n_s32 |
| #define simde_vqrshrn_high_n_s64 vqrshrn_high_n_s64 |
| #define simde_vqrshrn_high_n_u16 vqrshrn_high_n_u16 |
| #define simde_vqrshrn_high_n_u32 vqrshrn_high_n_u32 |
| #define simde_vqrshrn_high_n_u64 vqrshrn_high_n_u64 |
| #define simde_vqrshrn_n_s16 vqrshrn_n_s16 |
| #define simde_vqrshrn_n_s32 vqrshrn_n_s32 |
| #define simde_vqrshrn_n_s64 vqrshrn_n_s64 |
| #define simde_vqrshrn_n_u16 vqrshrn_n_u16 |
| #define simde_vqrshrn_n_u32 vqrshrn_n_u32 |
| #define simde_vqrshrn_n_u64 vqrshrn_n_u64 |
| #define simde_vqrshrnd_n_s64 vqrshrnd_n_s64 |
| #define simde_vqrshrnd_n_u64 vqrshrnd_n_u64 |
| #define simde_vqrshrnh_n_s16 vqrshrnh_n_s16 |
| #define simde_vqrshrnh_n_u16 vqrshrnh_n_u16 |
| #define simde_vqrshrns_n_s32 vqrshrns_n_s32 |
| #define simde_vqrshrns_n_u32 vqrshrns_n_u32 |
| #define simde_vqrshrun_high_n_s16 vqrshrun_high_n_s16 |
| #define simde_vqrshrun_high_n_s32 vqrshrun_high_n_s32 |
| #define simde_vqrshrun_high_n_s64 vqrshrun_high_n_s64 |
| #define simde_vqrshrun_n_s16 vqrshrun_n_s16 |
| #define simde_vqrshrun_n_s32 vqrshrun_n_s32 |
| #define simde_vqrshrun_n_s64 vqrshrun_n_s64 |
| #define simde_vqrshrund_n_s64 vqrshrund_n_s64 |
| #define simde_vqrshrunh_n_s16 vqrshrunh_n_s16 |
| #define simde_vqrshruns_n_s32 vqrshruns_n_s32 |
| #define simde_vqshl_n_s16 vqshl_n_s16 |
| #define simde_vqshl_n_s32 vqshl_n_s32 |
| #define simde_vqshl_n_s64 vqshl_n_s64 |
| #define simde_vqshl_n_s8 vqshl_n_s8 |
| #define simde_vqshl_n_u16 vqshl_n_u16 |
| #define simde_vqshl_n_u32 vqshl_n_u32 |
| #define simde_vqshl_n_u64 vqshl_n_u64 |
| #define simde_vqshl_n_u8 vqshl_n_u8 |
| #define simde_vqshl_s16 vqshl_s16 |
| #define simde_vqshl_s32 vqshl_s32 |
| #define simde_vqshl_s64 vqshl_s64 |
| #define simde_vqshl_s8 vqshl_s8 |
| #define simde_vqshl_u16 vqshl_u16 |
| #define simde_vqshl_u32 vqshl_u32 |
| #define simde_vqshl_u64 vqshl_u64 |
| #define simde_vqshl_u8 vqshl_u8 |
| #define simde_vqshlb_n_s8 vqshlb_n_s8 |
| #define simde_vqshlb_n_u8 vqshlb_n_u8 |
| #define simde_vqshlb_s8 vqshlb_s8 |
| #define simde_vqshlb_u8 vqshlb_u8 |
| #define simde_vqshld_n_s64 vqshld_n_s64 |
| #define simde_vqshld_n_u64 vqshld_n_u64 |
| #define simde_vqshld_s64 vqshld_s64 |
| #define simde_vqshld_u64 vqshld_u64 |
| #define simde_vqshlh_n_s16 vqshlh_n_s16 |
| #define simde_vqshlh_n_u16 vqshlh_n_u16 |
| #define simde_vqshlh_s16 vqshlh_s16 |
| #define simde_vqshlh_u16 vqshlh_u16 |
| #define simde_vqshlq_n_s16 vqshlq_n_s16 |
| #define simde_vqshlq_n_s32 vqshlq_n_s32 |
| #define simde_vqshlq_n_s64 vqshlq_n_s64 |
| #define simde_vqshlq_n_s8 vqshlq_n_s8 |
| #define simde_vqshlq_n_u16 vqshlq_n_u16 |
| #define simde_vqshlq_n_u32 vqshlq_n_u32 |
| #define simde_vqshlq_n_u64 vqshlq_n_u64 |
| #define simde_vqshlq_n_u8 vqshlq_n_u8 |
| #define simde_vqshlq_s16 vqshlq_s16 |
| #define simde_vqshlq_s32 vqshlq_s32 |
| #define simde_vqshlq_s64 vqshlq_s64 |
| #define simde_vqshlq_s8 vqshlq_s8 |
| #define simde_vqshlq_u16 vqshlq_u16 |
| #define simde_vqshlq_u32 vqshlq_u32 |
| #define simde_vqshlq_u64 vqshlq_u64 |
| #define simde_vqshlq_u8 vqshlq_u8 |
| #define simde_vqshls_n_s32 vqshls_n_s32 |
| #define simde_vqshls_n_u32 vqshls_n_u32 |
| #define simde_vqshls_s32 vqshls_s32 |
| #define simde_vqshls_u32 vqshls_u32 |
| #define simde_vqshlu_n_s16 vqshlu_n_s16 |
| #define simde_vqshlu_n_s32 vqshlu_n_s32 |
| #define simde_vqshlu_n_s64 vqshlu_n_s64 |
| #define simde_vqshlu_n_s8 vqshlu_n_s8 |
| #define simde_vqshlub_n_s8 vqshlub_n_s8 |
| #define simde_vqshlud_n_s64 vqshlud_n_s64 |
| #define simde_vqshluh_n_s16 vqshluh_n_s16 |
| #define simde_vqshluq_n_s16 vqshluq_n_s16 |
| #define simde_vqshluq_n_s32 vqshluq_n_s32 |
| #define simde_vqshluq_n_s64 vqshluq_n_s64 |
| #define simde_vqshluq_n_s8 vqshluq_n_s8 |
| #define simde_vqshlus_n_s32 vqshlus_n_s32 |
| #define simde_vqshrn_high_n_s16 vqshrn_high_n_s16 |
| #define simde_vqshrn_high_n_s32 vqshrn_high_n_s32 |
| #define simde_vqshrn_high_n_s64 vqshrn_high_n_s64 |
| #define simde_vqshrn_high_n_u16 vqshrn_high_n_u16 |
| #define simde_vqshrn_high_n_u32 vqshrn_high_n_u32 |
| #define simde_vqshrn_high_n_u64 vqshrn_high_n_u64 |
| #define simde_vqshrn_n_s16 vqshrn_n_s16 |
| #define simde_vqshrn_n_s32 vqshrn_n_s32 |
| #define simde_vqshrn_n_s64 vqshrn_n_s64 |
| #define simde_vqshrn_n_u16 vqshrn_n_u16 |
| #define simde_vqshrn_n_u32 vqshrn_n_u32 |
| #define simde_vqshrn_n_u64 vqshrn_n_u64 |
| #define simde_vqshrnd_n_s64 vqshrnd_n_s64 |
| #define simde_vqshrnd_n_u64 vqshrnd_n_u64 |
| #define simde_vqshrnh_n_s16 vqshrnh_n_s16 |
| #define simde_vqshrnh_n_u16 vqshrnh_n_u16 |
| #define simde_vqshrns_n_s32 vqshrns_n_s32 |
| #define simde_vqshrns_n_u32 vqshrns_n_u32 |
| #define simde_vqshrun_high_n_s16 vqshrun_high_n_s16 |
| #define simde_vqshrun_high_n_s32 vqshrun_high_n_s32 |
| #define simde_vqshrun_high_n_s64 vqshrun_high_n_s64 |
| #define simde_vqshrun_n_s16 vqshrun_n_s16 |
| #define simde_vqshrun_n_s32 vqshrun_n_s32 |
| #define simde_vqshrun_n_s64 vqshrun_n_s64 |
| #define simde_vqshrund_n_s64 vqshrund_n_s64 |
| #define simde_vqshrunh_n_s16 vqshrunh_n_s16 |
| #define simde_vqshruns_n_s32 vqshruns_n_s32 |
| #define simde_vqsub_s16 vqsub_s16 |
| #define simde_vqsub_s32 vqsub_s32 |
| #define simde_vqsub_s64 vqsub_s64 |
| #define simde_vqsub_s8 vqsub_s8 |
| #define simde_vqsub_u16 vqsub_u16 |
| #define simde_vqsub_u32 vqsub_u32 |
| #define simde_vqsub_u64 vqsub_u64 |
| #define simde_vqsub_u8 vqsub_u8 |
| #define simde_vqsubb_s8 vqsubb_s8 |
| #define simde_vqsubb_u8 vqsubb_u8 |
| #define simde_vqsubd_s64 vqsubd_s64 |
| #define simde_vqsubd_u64 vqsubd_u64 |
| #define simde_vqsubh_s16 vqsubh_s16 |
| #define simde_vqsubh_u16 vqsubh_u16 |
| #define simde_vqsubq_s16 vqsubq_s16 |
| #define simde_vqsubq_s32 vqsubq_s32 |
| #define simde_vqsubq_s64 vqsubq_s64 |
| #define simde_vqsubq_s8 vqsubq_s8 |
| #define simde_vqsubq_u16 vqsubq_u16 |
| #define simde_vqsubq_u32 vqsubq_u32 |
| #define simde_vqsubq_u64 vqsubq_u64 |
| #define simde_vqsubq_u8 vqsubq_u8 |
| #define simde_vqsubs_s32 vqsubs_s32 |
| #define simde_vqsubs_u32 vqsubs_u32 |
| #define simde_vqtbl1_p8 vqtbl1_p8 |
| #define simde_vqtbl1_s8 vqtbl1_s8 |
| #define simde_vqtbl1_u8 vqtbl1_u8 |
| #define simde_vqtbl1q_p8 vqtbl1q_p8 |
| #define simde_vqtbl1q_s8 vqtbl1q_s8 |
| #define simde_vqtbl1q_u8 vqtbl1q_u8 |
| #define simde_vqtbl2_p8 vqtbl2_p8 |
| #define simde_vqtbl2_s8 vqtbl2_s8 |
| #define simde_vqtbl2_u8 vqtbl2_u8 |
| #define simde_vqtbl2q_p8 vqtbl2q_p8 |
| #define simde_vqtbl2q_s8 vqtbl2q_s8 |
| #define simde_vqtbl2q_u8 vqtbl2q_u8 |
| #define simde_vqtbl3_p8 vqtbl3_p8 |
| #define simde_vqtbl3_s8 vqtbl3_s8 |
| #define simde_vqtbl3_u8 vqtbl3_u8 |
| #define simde_vqtbl3q_p8 vqtbl3q_p8 |
| #define simde_vqtbl3q_s8 vqtbl3q_s8 |
| #define simde_vqtbl3q_u8 vqtbl3q_u8 |
| #define simde_vqtbl4_p8 vqtbl4_p8 |
| #define simde_vqtbl4_s8 vqtbl4_s8 |
| #define simde_vqtbl4_u8 vqtbl4_u8 |
| #define simde_vqtbl4q_p8 vqtbl4q_p8 |
| #define simde_vqtbl4q_s8 vqtbl4q_s8 |
| #define simde_vqtbl4q_u8 vqtbl4q_u8 |
| #define simde_vqtbx1_p8 vqtbx1_p8 |
| #define simde_vqtbx1_s8 vqtbx1_s8 |
| #define simde_vqtbx1_u8 vqtbx1_u8 |
| #define simde_vqtbx1q_p8 vqtbx1q_p8 |
| #define simde_vqtbx1q_s8 vqtbx1q_s8 |
| #define simde_vqtbx1q_u8 vqtbx1q_u8 |
| #define simde_vqtbx2_p8 vqtbx2_p8 |
| #define simde_vqtbx2_s8 vqtbx2_s8 |
| #define simde_vqtbx2_u8 vqtbx2_u8 |
| #define simde_vqtbx2q_p8 vqtbx2q_p8 |
| #define simde_vqtbx2q_s8 vqtbx2q_s8 |
| #define simde_vqtbx2q_u8 vqtbx2q_u8 |
| #define simde_vqtbx3_p8 vqtbx3_p8 |
| #define simde_vqtbx3_s8 vqtbx3_s8 |
| #define simde_vqtbx3_u8 vqtbx3_u8 |
| #define simde_vqtbx3q_p8 vqtbx3q_p8 |
| #define simde_vqtbx3q_s8 vqtbx3q_s8 |
| #define simde_vqtbx3q_u8 vqtbx3q_u8 |
| #define simde_vqtbx4_p8 vqtbx4_p8 |
| #define simde_vqtbx4_s8 vqtbx4_s8 |
| #define simde_vqtbx4_u8 vqtbx4_u8 |
| #define simde_vqtbx4q_p8 vqtbx4q_p8 |
| #define simde_vqtbx4q_s8 vqtbx4q_s8 |
| #define simde_vqtbx4q_u8 vqtbx4q_u8 |
| #define simde_vraddhn_high_s16 vraddhn_high_s16 |
| #define simde_vraddhn_high_s32 vraddhn_high_s32 |
| #define simde_vraddhn_high_s64 vraddhn_high_s64 |
| #define simde_vraddhn_high_u16 vraddhn_high_u16 |
| #define simde_vraddhn_high_u32 vraddhn_high_u32 |
| #define simde_vraddhn_high_u64 vraddhn_high_u64 |
| #define simde_vraddhn_s16 vraddhn_s16 |
| #define simde_vraddhn_s32 vraddhn_s32 |
| #define simde_vraddhn_s64 vraddhn_s64 |
| #define simde_vraddhn_u16 vraddhn_u16 |
| #define simde_vraddhn_u32 vraddhn_u32 |
| #define simde_vraddhn_u64 vraddhn_u64 |
| #define simde_vrax1q_u64 vrax1q_u64 |
| #define simde_vrbit_p8 vrbit_p8 |
| #define simde_vrbit_s8 vrbit_s8 |
| #define simde_vrbit_u8 vrbit_u8 |
| #define simde_vrbitq_p8 vrbitq_p8 |
| #define simde_vrbitq_s8 vrbitq_s8 |
| #define simde_vrbitq_u8 vrbitq_u8 |
| #define simde_vrecpe_f16 vrecpe_f16 |
| #define simde_vrecpe_f32 vrecpe_f32 |
| #define simde_vrecpe_f64 vrecpe_f64 |
| #define simde_vrecpe_u32 vrecpe_u32 |
| #define simde_vrecped_f64 vrecped_f64 |
| #define simde_vrecpeq_f16 vrecpeq_f16 |
| #define simde_vrecpeq_f32 vrecpeq_f32 |
| #define simde_vrecpeq_f64 vrecpeq_f64 |
| #define simde_vrecpeq_u32 vrecpeq_u32 |
| #define simde_vrecpes_f32 vrecpes_f32 |
| #define simde_vrecps_f16 vrecps_f16 |
| #define simde_vrecps_f32 vrecps_f32 |
| #define simde_vrecps_f64 vrecps_f64 |
| #define simde_vrecpsd_f64 vrecpsd_f64 |
| #define simde_vrecpsq_f16 vrecpsq_f16 |
| #define simde_vrecpsq_f32 vrecpsq_f32 |
| #define simde_vrecpsq_f64 vrecpsq_f64 |
| #define simde_vrecpss_f32 vrecpss_f32 |
| #define simde_vrecpxd_f64 vrecpxd_f64 |
| #define simde_vrecpxs_f32 vrecpxs_f32 |
| #define simde_vreinterpret_bf16_f32 vreinterpret_bf16_f32 |
| #define simde_vreinterpret_bf16_f64 vreinterpret_bf16_f64 |
| #define simde_vreinterpret_bf16_p16 vreinterpret_bf16_p16 |
| #define simde_vreinterpret_bf16_p64 vreinterpret_bf16_p64 |
| #define simde_vreinterpret_bf16_p8 vreinterpret_bf16_p8 |
| #define simde_vreinterpret_bf16_s16 vreinterpret_bf16_s16 |
| #define simde_vreinterpret_bf16_s32 vreinterpret_bf16_s32 |
| #define simde_vreinterpret_bf16_s64 vreinterpret_bf16_s64 |
| #define simde_vreinterpret_bf16_s8 vreinterpret_bf16_s8 |
| #define simde_vreinterpret_bf16_u16 vreinterpret_bf16_u16 |
| #define simde_vreinterpret_bf16_u32 vreinterpret_bf16_u32 |
| #define simde_vreinterpret_bf16_u64 vreinterpret_bf16_u64 |
| #define simde_vreinterpret_bf16_u8 vreinterpret_bf16_u8 |
| #define simde_vreinterpret_f16_f32 vreinterpret_f16_f32 |
| #define simde_vreinterpret_f16_f64 vreinterpret_f16_f64 |
| #define simde_vreinterpret_f16_p16 vreinterpret_f16_p16 |
| #define simde_vreinterpret_f16_p64 vreinterpret_f16_p64 |
| #define simde_vreinterpret_f16_p8 vreinterpret_f16_p8 |
| #define simde_vreinterpret_f16_s16 vreinterpret_f16_s16 |
| #define simde_vreinterpret_f16_s32 vreinterpret_f16_s32 |
| #define simde_vreinterpret_f16_s64 vreinterpret_f16_s64 |
| #define simde_vreinterpret_f16_s8 vreinterpret_f16_s8 |
| #define simde_vreinterpret_f16_u16 vreinterpret_f16_u16 |
| #define simde_vreinterpret_f16_u32 vreinterpret_f16_u32 |
| #define simde_vreinterpret_f16_u64 vreinterpret_f16_u64 |
| #define simde_vreinterpret_f16_u8 vreinterpret_f16_u8 |
| #define simde_vreinterpret_f32_bf16 vreinterpret_f32_bf16 |
| #define simde_vreinterpret_f32_f16 vreinterpret_f32_f16 |
| #define simde_vreinterpret_f32_f64 vreinterpret_f32_f64 |
| #define simde_vreinterpret_f32_p16 vreinterpret_f32_p16 |
| #define simde_vreinterpret_f32_p8 vreinterpret_f32_p8 |
| #define simde_vreinterpret_f32_s16 vreinterpret_f32_s16 |
| #define simde_vreinterpret_f32_s32 vreinterpret_f32_s32 |
| #define simde_vreinterpret_f32_s64 vreinterpret_f32_s64 |
| #define simde_vreinterpret_f32_s8 vreinterpret_f32_s8 |
| #define simde_vreinterpret_f32_u16 vreinterpret_f32_u16 |
| #define simde_vreinterpret_f32_u32 vreinterpret_f32_u32 |
| #define simde_vreinterpret_f32_u64 vreinterpret_f32_u64 |
| #define simde_vreinterpret_f32_u8 vreinterpret_f32_u8 |
| #define simde_vreinterpret_f64_bf16 vreinterpret_f64_bf16 |
| #define simde_vreinterpret_f64_f16 vreinterpret_f64_f16 |
| #define simde_vreinterpret_f64_f32 vreinterpret_f64_f32 |
| #define simde_vreinterpret_f64_p16 vreinterpret_f64_p16 |
| #define simde_vreinterpret_f64_p64 vreinterpret_f64_p64 |
| #define simde_vreinterpret_f64_p8 vreinterpret_f64_p8 |
| #define simde_vreinterpret_f64_s16 vreinterpret_f64_s16 |
| #define simde_vreinterpret_f64_s32 vreinterpret_f64_s32 |
| #define simde_vreinterpret_f64_s64 vreinterpret_f64_s64 |
| #define simde_vreinterpret_f64_s8 vreinterpret_f64_s8 |
| #define simde_vreinterpret_f64_u16 vreinterpret_f64_u16 |
| #define simde_vreinterpret_f64_u32 vreinterpret_f64_u32 |
| #define simde_vreinterpret_f64_u64 vreinterpret_f64_u64 |
| #define simde_vreinterpret_f64_u8 vreinterpret_f64_u8 |
| #define simde_vreinterpret_p16_bf16 vreinterpret_p16_bf16 |
| #define simde_vreinterpret_p16_f16 vreinterpret_p16_f16 |
| #define simde_vreinterpret_p16_f32 vreinterpret_p16_f32 |
| #define simde_vreinterpret_p16_f64 vreinterpret_p16_f64 |
| #define simde_vreinterpret_p16_p64 vreinterpret_p16_p64 |
| #define simde_vreinterpret_p16_p8 vreinterpret_p16_p8 |
| #define simde_vreinterpret_p16_s16 vreinterpret_p16_s16 |
| #define simde_vreinterpret_p16_s32 vreinterpret_p16_s32 |
| #define simde_vreinterpret_p16_s64 vreinterpret_p16_s64 |
| #define simde_vreinterpret_p16_s8 vreinterpret_p16_s8 |
| #define simde_vreinterpret_p16_u16 vreinterpret_p16_u16 |
| #define simde_vreinterpret_p16_u32 vreinterpret_p16_u32 |
| #define simde_vreinterpret_p16_u64 vreinterpret_p16_u64 |
| #define simde_vreinterpret_p16_u8 vreinterpret_p16_u8 |
| #define simde_vreinterpret_p64_bf16 vreinterpret_p64_bf16 |
| #define simde_vreinterpret_p64_f16 vreinterpret_p64_f16 |
| #define simde_vreinterpret_p64_f32 vreinterpret_p64_f32 |
| #define simde_vreinterpret_p64_f64 vreinterpret_p64_f64 |
| #define simde_vreinterpret_p64_p16 vreinterpret_p64_p16 |
| #define simde_vreinterpret_p64_p8 vreinterpret_p64_p8 |
| #define simde_vreinterpret_p64_s16 vreinterpret_p64_s16 |
| #define simde_vreinterpret_p64_s32 vreinterpret_p64_s32 |
| #define simde_vreinterpret_p64_s8 vreinterpret_p64_s8 |
| #define simde_vreinterpret_p64_u16 vreinterpret_p64_u16 |
| #define simde_vreinterpret_p64_u32 vreinterpret_p64_u32 |
| #define simde_vreinterpret_p64_u64 vreinterpret_p64_u64 |
| #define simde_vreinterpret_p64_u8 vreinterpret_p64_u8 |
| #define simde_vreinterpret_p8_bf16 vreinterpret_p8_bf16 |
| #define simde_vreinterpret_p8_f16 vreinterpret_p8_f16 |
| #define simde_vreinterpret_p8_f32 vreinterpret_p8_f32 |
| #define simde_vreinterpret_p8_f64 vreinterpret_p8_f64 |
| #define simde_vreinterpret_p8_p16 vreinterpret_p8_p16 |
| #define simde_vreinterpret_p8_p64 vreinterpret_p8_p64 |
| #define simde_vreinterpret_p8_s16 vreinterpret_p8_s16 |
| #define simde_vreinterpret_p8_s32 vreinterpret_p8_s32 |
| #define simde_vreinterpret_p8_s64 vreinterpret_p8_s64 |
| #define simde_vreinterpret_p8_s8 vreinterpret_p8_s8 |
| #define simde_vreinterpret_p8_u16 vreinterpret_p8_u16 |
| #define simde_vreinterpret_p8_u32 vreinterpret_p8_u32 |
| #define simde_vreinterpret_p8_u64 vreinterpret_p8_u64 |
| #define simde_vreinterpret_p8_u8 vreinterpret_p8_u8 |
| #define simde_vreinterpret_s16_bf16 vreinterpret_s16_bf16 |
| #define simde_vreinterpret_s16_f16 vreinterpret_s16_f16 |
| #define simde_vreinterpret_s16_f32 vreinterpret_s16_f32 |
| #define simde_vreinterpret_s16_f64 vreinterpret_s16_f64 |
| #define simde_vreinterpret_s16_p16 vreinterpret_s16_p16 |
| #define simde_vreinterpret_s16_p64 vreinterpret_s16_p64 |
| #define simde_vreinterpret_s16_p8 vreinterpret_s16_p8 |
| #define simde_vreinterpret_s16_s32 vreinterpret_s16_s32 |
| #define simde_vreinterpret_s16_s64 vreinterpret_s16_s64 |
| #define simde_vreinterpret_s16_s8 vreinterpret_s16_s8 |
| #define simde_vreinterpret_s16_u16 vreinterpret_s16_u16 |
| #define simde_vreinterpret_s16_u32 vreinterpret_s16_u32 |
| #define simde_vreinterpret_s16_u64 vreinterpret_s16_u64 |
| #define simde_vreinterpret_s16_u8 vreinterpret_s16_u8 |
| #define simde_vreinterpret_s32_bf16 vreinterpret_s32_bf16 |
| #define simde_vreinterpret_s32_f16 vreinterpret_s32_f16 |
| #define simde_vreinterpret_s32_f32 vreinterpret_s32_f32 |
| #define simde_vreinterpret_s32_f64 vreinterpret_s32_f64 |
| #define simde_vreinterpret_s32_p16 vreinterpret_s32_p16 |
| #define simde_vreinterpret_s32_p64 vreinterpret_s32_p64 |
| #define simde_vreinterpret_s32_p8 vreinterpret_s32_p8 |
| #define simde_vreinterpret_s32_s16 vreinterpret_s32_s16 |
| #define simde_vreinterpret_s32_s64 vreinterpret_s32_s64 |
| #define simde_vreinterpret_s32_s8 vreinterpret_s32_s8 |
| #define simde_vreinterpret_s32_u16 vreinterpret_s32_u16 |
| #define simde_vreinterpret_s32_u32 vreinterpret_s32_u32 |
| #define simde_vreinterpret_s32_u64 vreinterpret_s32_u64 |
| #define simde_vreinterpret_s32_u8 vreinterpret_s32_u8 |
| #define simde_vreinterpret_s64_bf16 vreinterpret_s64_bf16 |
| #define simde_vreinterpret_s64_f16 vreinterpret_s64_f16 |
| #define simde_vreinterpret_s64_f32 vreinterpret_s64_f32 |
| #define simde_vreinterpret_s64_f64 vreinterpret_s64_f64 |
| #define simde_vreinterpret_s64_p16 vreinterpret_s64_p16 |
| #define simde_vreinterpret_s64_p64 vreinterpret_s64_p64 |
| #define simde_vreinterpret_s64_p8 vreinterpret_s64_p8 |
| #define simde_vreinterpret_s64_s16 vreinterpret_s64_s16 |
| #define simde_vreinterpret_s64_s32 vreinterpret_s64_s32 |
| #define simde_vreinterpret_s64_s8 vreinterpret_s64_s8 |
| #define simde_vreinterpret_s64_u16 vreinterpret_s64_u16 |
| #define simde_vreinterpret_s64_u32 vreinterpret_s64_u32 |
| #define simde_vreinterpret_s64_u64 vreinterpret_s64_u64 |
| #define simde_vreinterpret_s64_u8 vreinterpret_s64_u8 |
| #define simde_vreinterpret_s8_bf16 vreinterpret_s8_bf16 |
| #define simde_vreinterpret_s8_f16 vreinterpret_s8_f16 |
| #define simde_vreinterpret_s8_f32 vreinterpret_s8_f32 |
| #define simde_vreinterpret_s8_f64 vreinterpret_s8_f64 |
| #define simde_vreinterpret_s8_p16 vreinterpret_s8_p16 |
| #define simde_vreinterpret_s8_p64 vreinterpret_s8_p64 |
| #define simde_vreinterpret_s8_p8 vreinterpret_s8_p8 |
| #define simde_vreinterpret_s8_s16 vreinterpret_s8_s16 |
| #define simde_vreinterpret_s8_s32 vreinterpret_s8_s32 |
| #define simde_vreinterpret_s8_s64 vreinterpret_s8_s64 |
| #define simde_vreinterpret_s8_u16 vreinterpret_s8_u16 |
| #define simde_vreinterpret_s8_u32 vreinterpret_s8_u32 |
| #define simde_vreinterpret_s8_u64 vreinterpret_s8_u64 |
| #define simde_vreinterpret_s8_u8 vreinterpret_s8_u8 |
| #define simde_vreinterpret_u16_bf16 vreinterpret_u16_bf16 |
| #define simde_vreinterpret_u16_f16 vreinterpret_u16_f16 |
| #define simde_vreinterpret_u16_f32 vreinterpret_u16_f32 |
| #define simde_vreinterpret_u16_f64 vreinterpret_u16_f64 |
| #define simde_vreinterpret_u16_p16 vreinterpret_u16_p16 |
| #define simde_vreinterpret_u16_p64 vreinterpret_u16_p64 |
| #define simde_vreinterpret_u16_p8 vreinterpret_u16_p8 |
| #define simde_vreinterpret_u16_s16 vreinterpret_u16_s16 |
| #define simde_vreinterpret_u16_s32 vreinterpret_u16_s32 |
| #define simde_vreinterpret_u16_s64 vreinterpret_u16_s64 |
| #define simde_vreinterpret_u16_s8 vreinterpret_u16_s8 |
| #define simde_vreinterpret_u16_u32 vreinterpret_u16_u32 |
| #define simde_vreinterpret_u16_u64 vreinterpret_u16_u64 |
| #define simde_vreinterpret_u16_u8 vreinterpret_u16_u8 |
| #define simde_vreinterpret_u32_bf16 vreinterpret_u32_bf16 |
| #define simde_vreinterpret_u32_f16 vreinterpret_u32_f16 |
| #define simde_vreinterpret_u32_f32 vreinterpret_u32_f32 |
| #define simde_vreinterpret_u32_f64 vreinterpret_u32_f64 |
| #define simde_vreinterpret_u32_p16 vreinterpret_u32_p16 |
| #define simde_vreinterpret_u32_p64 vreinterpret_u32_p64 |
| #define simde_vreinterpret_u32_p8 vreinterpret_u32_p8 |
| #define simde_vreinterpret_u32_s16 vreinterpret_u32_s16 |
| #define simde_vreinterpret_u32_s32 vreinterpret_u32_s32 |
| #define simde_vreinterpret_u32_s64 vreinterpret_u32_s64 |
| #define simde_vreinterpret_u32_s8 vreinterpret_u32_s8 |
| #define simde_vreinterpret_u32_u16 vreinterpret_u32_u16 |
| #define simde_vreinterpret_u32_u64 vreinterpret_u32_u64 |
| #define simde_vreinterpret_u32_u8 vreinterpret_u32_u8 |
| #define simde_vreinterpret_u64_bf16 vreinterpret_u64_bf16 |
| #define simde_vreinterpret_u64_f16 vreinterpret_u64_f16 |
| #define simde_vreinterpret_u64_f32 vreinterpret_u64_f32 |
| #define simde_vreinterpret_u64_f64 vreinterpret_u64_f64 |
| #define simde_vreinterpret_u64_p16 vreinterpret_u64_p16 |
| #define simde_vreinterpret_u64_p64 vreinterpret_u64_p64 |
| #define simde_vreinterpret_u64_p8 vreinterpret_u64_p8 |
| #define simde_vreinterpret_u64_s16 vreinterpret_u64_s16 |
| #define simde_vreinterpret_u64_s32 vreinterpret_u64_s32 |
| #define simde_vreinterpret_u64_s64 vreinterpret_u64_s64 |
| #define simde_vreinterpret_u64_s8 vreinterpret_u64_s8 |
| #define simde_vreinterpret_u64_u16 vreinterpret_u64_u16 |
| #define simde_vreinterpret_u64_u32 vreinterpret_u64_u32 |
| #define simde_vreinterpret_u64_u8 vreinterpret_u64_u8 |
| #define simde_vreinterpret_u8_bf16 vreinterpret_u8_bf16 |
| #define simde_vreinterpret_u8_f16 vreinterpret_u8_f16 |
| #define simde_vreinterpret_u8_f32 vreinterpret_u8_f32 |
| #define simde_vreinterpret_u8_f64 vreinterpret_u8_f64 |
| #define simde_vreinterpret_u8_p16 vreinterpret_u8_p16 |
| #define simde_vreinterpret_u8_p64 vreinterpret_u8_p64 |
| #define simde_vreinterpret_u8_p8 vreinterpret_u8_p8 |
| #define simde_vreinterpret_u8_s16 vreinterpret_u8_s16 |
| #define simde_vreinterpret_u8_s32 vreinterpret_u8_s32 |
| #define simde_vreinterpret_u8_s64 vreinterpret_u8_s64 |
| #define simde_vreinterpret_u8_s8 vreinterpret_u8_s8 |
| #define simde_vreinterpret_u8_u16 vreinterpret_u8_u16 |
| #define simde_vreinterpret_u8_u32 vreinterpret_u8_u32 |
| #define simde_vreinterpret_u8_u64 vreinterpret_u8_u64 |
| #define simde_vreinterpretq_bf16_f32 vreinterpretq_bf16_f32 |
| #define simde_vreinterpretq_bf16_f64 vreinterpretq_bf16_f64 |
| #define simde_vreinterpretq_bf16_p128 vreinterpretq_bf16_p128 |
| #define simde_vreinterpretq_bf16_p16 vreinterpretq_bf16_p16 |
| #define simde_vreinterpretq_bf16_p64 vreinterpretq_bf16_p64 |
| #define simde_vreinterpretq_bf16_p8 vreinterpretq_bf16_p8 |
| #define simde_vreinterpretq_bf16_s16 vreinterpretq_bf16_s16 |
| #define simde_vreinterpretq_bf16_s32 vreinterpretq_bf16_s32 |
| #define simde_vreinterpretq_bf16_s64 vreinterpretq_bf16_s64 |
| #define simde_vreinterpretq_bf16_s8 vreinterpretq_bf16_s8 |
| #define simde_vreinterpretq_bf16_u16 vreinterpretq_bf16_u16 |
| #define simde_vreinterpretq_bf16_u32 vreinterpretq_bf16_u32 |
| #define simde_vreinterpretq_bf16_u64 vreinterpretq_bf16_u64 |
| #define simde_vreinterpretq_bf16_u8 vreinterpretq_bf16_u8 |
| #define simde_vreinterpretq_f16_f32 vreinterpretq_f16_f32 |
| #define simde_vreinterpretq_f16_f64 vreinterpretq_f16_f64 |
| #define simde_vreinterpretq_f16_p128 vreinterpretq_f16_p128 |
| #define simde_vreinterpretq_f16_p16 vreinterpretq_f16_p16 |
| #define simde_vreinterpretq_f16_p64 vreinterpretq_f16_p64 |
| #define simde_vreinterpretq_f16_p8 vreinterpretq_f16_p8 |
| #define simde_vreinterpretq_f16_s16 vreinterpretq_f16_s16 |
| #define simde_vreinterpretq_f16_s32 vreinterpretq_f16_s32 |
| #define simde_vreinterpretq_f16_s64 vreinterpretq_f16_s64 |
| #define simde_vreinterpretq_f16_s8 vreinterpretq_f16_s8 |
| #define simde_vreinterpretq_f16_u16 vreinterpretq_f16_u16 |
| #define simde_vreinterpretq_f16_u32 vreinterpretq_f16_u32 |
| #define simde_vreinterpretq_f16_u64 vreinterpretq_f16_u64 |
| #define simde_vreinterpretq_f16_u8 vreinterpretq_f16_u8 |
| #define simde_vreinterpretq_f32_bf16 vreinterpretq_f32_bf16 |
| #define simde_vreinterpretq_f32_f16 vreinterpretq_f32_f16 |
| #define simde_vreinterpretq_f32_f64 vreinterpretq_f32_f64 |
| #define simde_vreinterpretq_f32_p16 vreinterpretq_f32_p16 |
| #define simde_vreinterpretq_f32_p8 vreinterpretq_f32_p8 |
| #define simde_vreinterpretq_f32_s16 vreinterpretq_f32_s16 |
| #define simde_vreinterpretq_f32_s32 vreinterpretq_f32_s32 |
| #define simde_vreinterpretq_f32_s64 vreinterpretq_f32_s64 |
| #define simde_vreinterpretq_f32_s8 vreinterpretq_f32_s8 |
| #define simde_vreinterpretq_f32_u16 vreinterpretq_f32_u16 |
| #define simde_vreinterpretq_f32_u32 vreinterpretq_f32_u32 |
| #define simde_vreinterpretq_f32_u64 vreinterpretq_f32_u64 |
| #define simde_vreinterpretq_f32_u8 vreinterpretq_f32_u8 |
| #define simde_vreinterpretq_f64_bf16 vreinterpretq_f64_bf16 |
| #define simde_vreinterpretq_f64_f16 vreinterpretq_f64_f16 |
| #define simde_vreinterpretq_f64_f32 vreinterpretq_f64_f32 |
| #define simde_vreinterpretq_f64_p128 vreinterpretq_f64_p128 |
| #define simde_vreinterpretq_f64_p16 vreinterpretq_f64_p16 |
| #define simde_vreinterpretq_f64_p64 vreinterpretq_f64_p64 |
| #define simde_vreinterpretq_f64_p8 vreinterpretq_f64_p8 |
| #define simde_vreinterpretq_f64_s16 vreinterpretq_f64_s16 |
| #define simde_vreinterpretq_f64_s32 vreinterpretq_f64_s32 |
| #define simde_vreinterpretq_f64_s64 vreinterpretq_f64_s64 |
| #define simde_vreinterpretq_f64_s8 vreinterpretq_f64_s8 |
| #define simde_vreinterpretq_f64_u16 vreinterpretq_f64_u16 |
| #define simde_vreinterpretq_f64_u32 vreinterpretq_f64_u32 |
| #define simde_vreinterpretq_f64_u64 vreinterpretq_f64_u64 |
| #define simde_vreinterpretq_f64_u8 vreinterpretq_f64_u8 |
| #define simde_vreinterpretq_p128_bf16 vreinterpretq_p128_bf16 |
| #define simde_vreinterpretq_p128_f16 vreinterpretq_p128_f16 |
| #define simde_vreinterpretq_p128_f32 vreinterpretq_p128_f32 |
| #define simde_vreinterpretq_p128_f64 vreinterpretq_p128_f64 |
| #define simde_vreinterpretq_p128_p16 vreinterpretq_p128_p16 |
| #define simde_vreinterpretq_p128_p8 vreinterpretq_p128_p8 |
| #define simde_vreinterpretq_p128_s16 vreinterpretq_p128_s16 |
| #define simde_vreinterpretq_p128_s32 vreinterpretq_p128_s32 |
| #define simde_vreinterpretq_p128_s64 vreinterpretq_p128_s64 |
| #define simde_vreinterpretq_p128_s8 vreinterpretq_p128_s8 |
| #define simde_vreinterpretq_p128_u16 vreinterpretq_p128_u16 |
| #define simde_vreinterpretq_p128_u32 vreinterpretq_p128_u32 |
| #define simde_vreinterpretq_p128_u64 vreinterpretq_p128_u64 |
| #define simde_vreinterpretq_p128_u8 vreinterpretq_p128_u8 |
| #define simde_vreinterpretq_p16_bf16 vreinterpretq_p16_bf16 |
| #define simde_vreinterpretq_p16_f16 vreinterpretq_p16_f16 |
| #define simde_vreinterpretq_p16_f32 vreinterpretq_p16_f32 |
| #define simde_vreinterpretq_p16_f64 vreinterpretq_p16_f64 |
| #define simde_vreinterpretq_p16_p128 vreinterpretq_p16_p128 |
| #define simde_vreinterpretq_p16_p64 vreinterpretq_p16_p64 |
| #define simde_vreinterpretq_p16_p8 vreinterpretq_p16_p8 |
| #define simde_vreinterpretq_p16_s16 vreinterpretq_p16_s16 |
| #define simde_vreinterpretq_p16_s32 vreinterpretq_p16_s32 |
| #define simde_vreinterpretq_p16_s64 vreinterpretq_p16_s64 |
| #define simde_vreinterpretq_p16_s8 vreinterpretq_p16_s8 |
| #define simde_vreinterpretq_p16_u16 vreinterpretq_p16_u16 |
| #define simde_vreinterpretq_p16_u32 vreinterpretq_p16_u32 |
| #define simde_vreinterpretq_p16_u64 vreinterpretq_p16_u64 |
| #define simde_vreinterpretq_p16_u8 vreinterpretq_p16_u8 |
| #define simde_vreinterpretq_p64_bf16 vreinterpretq_p64_bf16 |
| #define simde_vreinterpretq_p64_f16 vreinterpretq_p64_f16 |
| #define simde_vreinterpretq_p64_f32 vreinterpretq_p64_f32 |
| #define simde_vreinterpretq_p64_f64 vreinterpretq_p64_f64 |
| #define simde_vreinterpretq_p64_p16 vreinterpretq_p64_p16 |
| #define simde_vreinterpretq_p64_p8 vreinterpretq_p64_p8 |
| #define simde_vreinterpretq_p64_s16 vreinterpretq_p64_s16 |
| #define simde_vreinterpretq_p64_s32 vreinterpretq_p64_s32 |
| #define simde_vreinterpretq_p64_s64 vreinterpretq_p64_s64 |
| #define simde_vreinterpretq_p64_s8 vreinterpretq_p64_s8 |
| #define simde_vreinterpretq_p64_u16 vreinterpretq_p64_u16 |
| #define simde_vreinterpretq_p64_u32 vreinterpretq_p64_u32 |
| #define simde_vreinterpretq_p64_u64 vreinterpretq_p64_u64 |
| #define simde_vreinterpretq_p64_u8 vreinterpretq_p64_u8 |
| #define simde_vreinterpretq_p8_bf16 vreinterpretq_p8_bf16 |
| #define simde_vreinterpretq_p8_f16 vreinterpretq_p8_f16 |
| #define simde_vreinterpretq_p8_f32 vreinterpretq_p8_f32 |
| #define simde_vreinterpretq_p8_f64 vreinterpretq_p8_f64 |
| #define simde_vreinterpretq_p8_p128 vreinterpretq_p8_p128 |
| #define simde_vreinterpretq_p8_p16 vreinterpretq_p8_p16 |
| #define simde_vreinterpretq_p8_p64 vreinterpretq_p8_p64 |
| #define simde_vreinterpretq_p8_s16 vreinterpretq_p8_s16 |
| #define simde_vreinterpretq_p8_s32 vreinterpretq_p8_s32 |
| #define simde_vreinterpretq_p8_s64 vreinterpretq_p8_s64 |
| #define simde_vreinterpretq_p8_s8 vreinterpretq_p8_s8 |
| #define simde_vreinterpretq_p8_u16 vreinterpretq_p8_u16 |
| #define simde_vreinterpretq_p8_u32 vreinterpretq_p8_u32 |
| #define simde_vreinterpretq_p8_u64 vreinterpretq_p8_u64 |
| #define simde_vreinterpretq_p8_u8 vreinterpretq_p8_u8 |
| #define simde_vreinterpretq_s16_bf16 vreinterpretq_s16_bf16 |
| #define simde_vreinterpretq_s16_f16 vreinterpretq_s16_f16 |
| #define simde_vreinterpretq_s16_f32 vreinterpretq_s16_f32 |
| #define simde_vreinterpretq_s16_f64 vreinterpretq_s16_f64 |
| #define simde_vreinterpretq_s16_p128 vreinterpretq_s16_p128 |
| #define simde_vreinterpretq_s16_p16 vreinterpretq_s16_p16 |
| #define simde_vreinterpretq_s16_p64 vreinterpretq_s16_p64 |
| #define simde_vreinterpretq_s16_p8 vreinterpretq_s16_p8 |
| #define simde_vreinterpretq_s16_s32 vreinterpretq_s16_s32 |
| #define simde_vreinterpretq_s16_s64 vreinterpretq_s16_s64 |
| #define simde_vreinterpretq_s16_s8 vreinterpretq_s16_s8 |
| #define simde_vreinterpretq_s16_u16 vreinterpretq_s16_u16 |
| #define simde_vreinterpretq_s16_u32 vreinterpretq_s16_u32 |
| #define simde_vreinterpretq_s16_u64 vreinterpretq_s16_u64 |
| #define simde_vreinterpretq_s16_u8 vreinterpretq_s16_u8 |
| #define simde_vreinterpretq_s32_bf16 vreinterpretq_s32_bf16 |
| #define simde_vreinterpretq_s32_f16 vreinterpretq_s32_f16 |
| #define simde_vreinterpretq_s32_f32 vreinterpretq_s32_f32 |
| #define simde_vreinterpretq_s32_f64 vreinterpretq_s32_f64 |
| #define simde_vreinterpretq_s32_p128 vreinterpretq_s32_p128 |
| #define simde_vreinterpretq_s32_p16 vreinterpretq_s32_p16 |
| #define simde_vreinterpretq_s32_p64 vreinterpretq_s32_p64 |
| #define simde_vreinterpretq_s32_p8 vreinterpretq_s32_p8 |
| #define simde_vreinterpretq_s32_s16 vreinterpretq_s32_s16 |
| #define simde_vreinterpretq_s32_s64 vreinterpretq_s32_s64 |
| #define simde_vreinterpretq_s32_s8 vreinterpretq_s32_s8 |
| #define simde_vreinterpretq_s32_u16 vreinterpretq_s32_u16 |
| #define simde_vreinterpretq_s32_u32 vreinterpretq_s32_u32 |
| #define simde_vreinterpretq_s32_u64 vreinterpretq_s32_u64 |
| #define simde_vreinterpretq_s32_u8 vreinterpretq_s32_u8 |
| #define simde_vreinterpretq_s64_bf16 vreinterpretq_s64_bf16 |
| #define simde_vreinterpretq_s64_f16 vreinterpretq_s64_f16 |
| #define simde_vreinterpretq_s64_f32 vreinterpretq_s64_f32 |
| #define simde_vreinterpretq_s64_f64 vreinterpretq_s64_f64 |
| #define simde_vreinterpretq_s64_p128 vreinterpretq_s64_p128 |
| #define simde_vreinterpretq_s64_p16 vreinterpretq_s64_p16 |
| #define simde_vreinterpretq_s64_p64 vreinterpretq_s64_p64 |
| #define simde_vreinterpretq_s64_p8 vreinterpretq_s64_p8 |
| #define simde_vreinterpretq_s64_s16 vreinterpretq_s64_s16 |
| #define simde_vreinterpretq_s64_s32 vreinterpretq_s64_s32 |
| #define simde_vreinterpretq_s64_s8 vreinterpretq_s64_s8 |
| #define simde_vreinterpretq_s64_u16 vreinterpretq_s64_u16 |
| #define simde_vreinterpretq_s64_u32 vreinterpretq_s64_u32 |
| #define simde_vreinterpretq_s64_u64 vreinterpretq_s64_u64 |
| #define simde_vreinterpretq_s64_u8 vreinterpretq_s64_u8 |
| #define simde_vreinterpretq_s8_bf16 vreinterpretq_s8_bf16 |
| #define simde_vreinterpretq_s8_f16 vreinterpretq_s8_f16 |
| #define simde_vreinterpretq_s8_f32 vreinterpretq_s8_f32 |
| #define simde_vreinterpretq_s8_f64 vreinterpretq_s8_f64 |
| #define simde_vreinterpretq_s8_p128 vreinterpretq_s8_p128 |
| #define simde_vreinterpretq_s8_p16 vreinterpretq_s8_p16 |
| #define simde_vreinterpretq_s8_p64 vreinterpretq_s8_p64 |
| #define simde_vreinterpretq_s8_p8 vreinterpretq_s8_p8 |
| #define simde_vreinterpretq_s8_s16 vreinterpretq_s8_s16 |
| #define simde_vreinterpretq_s8_s32 vreinterpretq_s8_s32 |
| #define simde_vreinterpretq_s8_s64 vreinterpretq_s8_s64 |
| #define simde_vreinterpretq_s8_u16 vreinterpretq_s8_u16 |
| #define simde_vreinterpretq_s8_u32 vreinterpretq_s8_u32 |
| #define simde_vreinterpretq_s8_u64 vreinterpretq_s8_u64 |
| #define simde_vreinterpretq_s8_u8 vreinterpretq_s8_u8 |
| #define simde_vreinterpretq_u16_bf16 vreinterpretq_u16_bf16 |
| #define simde_vreinterpretq_u16_f16 vreinterpretq_u16_f16 |
| #define simde_vreinterpretq_u16_f32 vreinterpretq_u16_f32 |
| #define simde_vreinterpretq_u16_f64 vreinterpretq_u16_f64 |
| #define simde_vreinterpretq_u16_p128 vreinterpretq_u16_p128 |
| #define simde_vreinterpretq_u16_p16 vreinterpretq_u16_p16 |
| #define simde_vreinterpretq_u16_p64 vreinterpretq_u16_p64 |
| #define simde_vreinterpretq_u16_p8 vreinterpretq_u16_p8 |
| #define simde_vreinterpretq_u16_s16 vreinterpretq_u16_s16 |
| #define simde_vreinterpretq_u16_s32 vreinterpretq_u16_s32 |
| #define simde_vreinterpretq_u16_s64 vreinterpretq_u16_s64 |
| #define simde_vreinterpretq_u16_s8 vreinterpretq_u16_s8 |
| #define simde_vreinterpretq_u16_u32 vreinterpretq_u16_u32 |
| #define simde_vreinterpretq_u16_u64 vreinterpretq_u16_u64 |
| #define simde_vreinterpretq_u16_u8 vreinterpretq_u16_u8 |
| #define simde_vreinterpretq_u32_bf16 vreinterpretq_u32_bf16 |
| #define simde_vreinterpretq_u32_f16 vreinterpretq_u32_f16 |
| #define simde_vreinterpretq_u32_f32 vreinterpretq_u32_f32 |
| #define simde_vreinterpretq_u32_f64 vreinterpretq_u32_f64 |
| #define simde_vreinterpretq_u32_p128 vreinterpretq_u32_p128 |
| #define simde_vreinterpretq_u32_p16 vreinterpretq_u32_p16 |
| #define simde_vreinterpretq_u32_p64 vreinterpretq_u32_p64 |
| #define simde_vreinterpretq_u32_p8 vreinterpretq_u32_p8 |
| #define simde_vreinterpretq_u32_s16 vreinterpretq_u32_s16 |
| #define simde_vreinterpretq_u32_s32 vreinterpretq_u32_s32 |
| #define simde_vreinterpretq_u32_s64 vreinterpretq_u32_s64 |
| #define simde_vreinterpretq_u32_s8 vreinterpretq_u32_s8 |
| #define simde_vreinterpretq_u32_u16 vreinterpretq_u32_u16 |
| #define simde_vreinterpretq_u32_u64 vreinterpretq_u32_u64 |
| #define simde_vreinterpretq_u32_u8 vreinterpretq_u32_u8 |
| #define simde_vreinterpretq_u64_bf16 vreinterpretq_u64_bf16 |
| #define simde_vreinterpretq_u64_f16 vreinterpretq_u64_f16 |
| #define simde_vreinterpretq_u64_f32 vreinterpretq_u64_f32 |
| #define simde_vreinterpretq_u64_f64 vreinterpretq_u64_f64 |
| #define simde_vreinterpretq_u64_p128 vreinterpretq_u64_p128 |
| #define simde_vreinterpretq_u64_p16 vreinterpretq_u64_p16 |
| #define simde_vreinterpretq_u64_p64 vreinterpretq_u64_p64 |
| #define simde_vreinterpretq_u64_p8 vreinterpretq_u64_p8 |
| #define simde_vreinterpretq_u64_s16 vreinterpretq_u64_s16 |
| #define simde_vreinterpretq_u64_s32 vreinterpretq_u64_s32 |
| #define simde_vreinterpretq_u64_s64 vreinterpretq_u64_s64 |
| #define simde_vreinterpretq_u64_s8 vreinterpretq_u64_s8 |
| #define simde_vreinterpretq_u64_u16 vreinterpretq_u64_u16 |
| #define simde_vreinterpretq_u64_u32 vreinterpretq_u64_u32 |
| #define simde_vreinterpretq_u64_u8 vreinterpretq_u64_u8 |
| #define simde_vreinterpretq_u8_bf16 vreinterpretq_u8_bf16 |
| #define simde_vreinterpretq_u8_f16 vreinterpretq_u8_f16 |
| #define simde_vreinterpretq_u8_f32 vreinterpretq_u8_f32 |
| #define simde_vreinterpretq_u8_f64 vreinterpretq_u8_f64 |
| #define simde_vreinterpretq_u8_p128 vreinterpretq_u8_p128 |
| #define simde_vreinterpretq_u8_p16 vreinterpretq_u8_p16 |
| #define simde_vreinterpretq_u8_p64 vreinterpretq_u8_p64 |
| #define simde_vreinterpretq_u8_p8 vreinterpretq_u8_p8 |
| #define simde_vreinterpretq_u8_s16 vreinterpretq_u8_s16 |
| #define simde_vreinterpretq_u8_s32 vreinterpretq_u8_s32 |
| #define simde_vreinterpretq_u8_s64 vreinterpretq_u8_s64 |
| #define simde_vreinterpretq_u8_s8 vreinterpretq_u8_s8 |
| #define simde_vreinterpretq_u8_u16 vreinterpretq_u8_u16 |
| #define simde_vreinterpretq_u8_u32 vreinterpretq_u8_u32 |
| #define simde_vreinterpretq_u8_u64 vreinterpretq_u8_u64 |
| #define simde_vrev16_p8 vrev16_p8 |
| #define simde_vrev16_s8 vrev16_s8 |
| #define simde_vrev16_u8 vrev16_u8 |
| #define simde_vrev16q_p8 vrev16q_p8 |
| #define simde_vrev16q_s8 vrev16q_s8 |
| #define simde_vrev16q_u8 vrev16q_u8 |
| #define simde_vrev32_p16 vrev32_p16 |
| #define simde_vrev32_p8 vrev32_p8 |
| #define simde_vrev32_s16 vrev32_s16 |
| #define simde_vrev32_s8 vrev32_s8 |
| #define simde_vrev32_u16 vrev32_u16 |
| #define simde_vrev32_u8 vrev32_u8 |
| #define simde_vrev32q_p16 vrev32q_p16 |
| #define simde_vrev32q_p8 vrev32q_p8 |
| #define simde_vrev32q_s16 vrev32q_s16 |
| #define simde_vrev32q_s8 vrev32q_s8 |
| #define simde_vrev32q_u16 vrev32q_u16 |
| #define simde_vrev32q_u8 vrev32q_u8 |
| #define simde_vrev64_f16 vrev64_f16 |
| #define simde_vrev64_f32 vrev64_f32 |
| #define simde_vrev64_p16 vrev64_p16 |
| #define simde_vrev64_p8 vrev64_p8 |
| #define simde_vrev64_s16 vrev64_s16 |
| #define simde_vrev64_s32 vrev64_s32 |
| #define simde_vrev64_s8 vrev64_s8 |
| #define simde_vrev64_u16 vrev64_u16 |
| #define simde_vrev64_u32 vrev64_u32 |
| #define simde_vrev64_u8 vrev64_u8 |
| #define simde_vrev64q_f16 vrev64q_f16 |
| #define simde_vrev64q_f32 vrev64q_f32 |
| #define simde_vrev64q_p16 vrev64q_p16 |
| #define simde_vrev64q_p8 vrev64q_p8 |
| #define simde_vrev64q_s16 vrev64q_s16 |
| #define simde_vrev64q_s32 vrev64q_s32 |
| #define simde_vrev64q_s8 vrev64q_s8 |
| #define simde_vrev64q_u16 vrev64q_u16 |
| #define simde_vrev64q_u32 vrev64q_u32 |
| #define simde_vrev64q_u8 vrev64q_u8 |
| #define simde_vrhadd_s16 vrhadd_s16 |
| #define simde_vrhadd_s32 vrhadd_s32 |
| #define simde_vrhadd_s8 vrhadd_s8 |
| #define simde_vrhadd_u16 vrhadd_u16 |
| #define simde_vrhadd_u32 vrhadd_u32 |
| #define simde_vrhadd_u8 vrhadd_u8 |
| #define simde_vrhaddq_s16 vrhaddq_s16 |
| #define simde_vrhaddq_s32 vrhaddq_s32 |
| #define simde_vrhaddq_s8 vrhaddq_s8 |
| #define simde_vrhaddq_u16 vrhaddq_u16 |
| #define simde_vrhaddq_u32 vrhaddq_u32 |
| #define simde_vrhaddq_u8 vrhaddq_u8 |
| #define simde_vrnd_f16 vrnd_f16 |
| #define simde_vrnd_f32 vrnd_f32 |
| #define simde_vrnd_f64 vrnd_f64 |
| #define simde_vrnd32x_f32 vrnd32x_f32 |
| #define simde_vrnd32x_f64 vrnd32x_f64 |
| #define simde_vrnd32xq_f32 vrnd32xq_f32 |
| #define simde_vrnd32xq_f64 vrnd32xq_f64 |
| #define simde_vrnd32z_f32 vrnd32z_f32 |
| #define simde_vrnd32z_f64 vrnd32z_f64 |
| #define simde_vrnd32zq_f32 vrnd32zq_f32 |
| #define simde_vrnd32zq_f64 vrnd32zq_f64 |
| #define simde_vrnd64x_f32 vrnd64x_f32 |
| #define simde_vrnd64x_f64 vrnd64x_f64 |
| #define simde_vrnd64xq_f32 vrnd64xq_f32 |
| #define simde_vrnd64xq_f64 vrnd64xq_f64 |
| #define simde_vrnd64z_f32 vrnd64z_f32 |
| #define simde_vrnd64z_f64 vrnd64z_f64 |
| #define simde_vrnd64zq_f32 vrnd64zq_f32 |
| #define simde_vrnd64zq_f64 vrnd64zq_f64 |
| #define simde_vrnda_f16 vrnda_f16 |
| #define simde_vrnda_f32 vrnda_f32 |
| #define simde_vrnda_f64 vrnda_f64 |
| #define simde_vrndaq_f16 vrndaq_f16 |
| #define simde_vrndaq_f32 vrndaq_f32 |
| #define simde_vrndaq_f64 vrndaq_f64 |
| #define simde_vrndi_f16 vrndi_f16 |
| #define simde_vrndi_f32 vrndi_f32 |
| #define simde_vrndi_f64 vrndi_f64 |
| #define simde_vrndiq_f16 vrndiq_f16 |
| #define simde_vrndiq_f32 vrndiq_f32 |
| #define simde_vrndiq_f64 vrndiq_f64 |
| #define simde_vrndm_f16 vrndm_f16 |
| #define simde_vrndm_f32 vrndm_f32 |
| #define simde_vrndm_f64 vrndm_f64 |
| #define simde_vrndmq_f16 vrndmq_f16 |
| #define simde_vrndmq_f32 vrndmq_f32 |
| #define simde_vrndmq_f64 vrndmq_f64 |
| #define simde_vrndn_f16 vrndn_f16 |
| #define simde_vrndn_f32 vrndn_f32 |
| #define simde_vrndn_f64 vrndn_f64 |
| #define simde_vrndnq_f16 vrndnq_f16 |
| #define simde_vrndnq_f32 vrndnq_f32 |
| #define simde_vrndnq_f64 vrndnq_f64 |
| #define simde_vrndns_f32 vrndns_f32 |
| #define simde_vrndp_f16 vrndp_f16 |
| #define simde_vrndp_f32 vrndp_f32 |
| #define simde_vrndp_f64 vrndp_f64 |
| #define simde_vrndpq_f16 vrndpq_f16 |
| #define simde_vrndpq_f32 vrndpq_f32 |
| #define simde_vrndpq_f64 vrndpq_f64 |
| #define simde_vrndq_f16 vrndq_f16 |
| #define simde_vrndq_f32 vrndq_f32 |
| #define simde_vrndq_f64 vrndq_f64 |
| #define simde_vrndx_f16 vrndx_f16 |
| #define simde_vrndx_f32 vrndx_f32 |
| #define simde_vrndx_f64 vrndx_f64 |
| #define simde_vrndxq_f16 vrndxq_f16 |
| #define simde_vrndxq_f32 vrndxq_f32 |
| #define simde_vrndxq_f64 vrndxq_f64 |
| #define simde_vrshl_s16 vrshl_s16 |
| #define simde_vrshl_s32 vrshl_s32 |
| #define simde_vrshl_s64 vrshl_s64 |
| #define simde_vrshl_s8 vrshl_s8 |
| #define simde_vrshl_u16 vrshl_u16 |
| #define simde_vrshl_u32 vrshl_u32 |
| #define simde_vrshl_u64 vrshl_u64 |
| #define simde_vrshl_u8 vrshl_u8 |
| #define simde_vrshld_s64 vrshld_s64 |
| #define simde_vrshld_u64 vrshld_u64 |
| #define simde_vrshlq_s16 vrshlq_s16 |
| #define simde_vrshlq_s32 vrshlq_s32 |
| #define simde_vrshlq_s64 vrshlq_s64 |
| #define simde_vrshlq_s8 vrshlq_s8 |
| #define simde_vrshlq_u16 vrshlq_u16 |
| #define simde_vrshlq_u32 vrshlq_u32 |
| #define simde_vrshlq_u64 vrshlq_u64 |
| #define simde_vrshlq_u8 vrshlq_u8 |
| #define simde_vrshr_n_s16 vrshr_n_s16 |
| #define simde_vrshr_n_s32 vrshr_n_s32 |
| #define simde_vrshr_n_s64 vrshr_n_s64 |
| #define simde_vrshr_n_s8 vrshr_n_s8 |
| #define simde_vrshr_n_u16 vrshr_n_u16 |
| #define simde_vrshr_n_u32 vrshr_n_u32 |
| #define simde_vrshr_n_u64 vrshr_n_u64 |
| #define simde_vrshr_n_u8 vrshr_n_u8 |
| #define simde_vrshrd_n_s64 vrshrd_n_s64 |
| #define simde_vrshrd_n_u64 vrshrd_n_u64 |
| #define simde_vrshrn_high_n_s16 vrshrn_high_n_s16 |
| #define simde_vrshrn_high_n_s32 vrshrn_high_n_s32 |
| #define simde_vrshrn_high_n_s64 vrshrn_high_n_s64 |
| #define simde_vrshrn_high_n_u16 vrshrn_high_n_u16 |
| #define simde_vrshrn_high_n_u32 vrshrn_high_n_u32 |
| #define simde_vrshrn_high_n_u64 vrshrn_high_n_u64 |
| #define simde_vrshrn_n_s16 vrshrn_n_s16 |
| #define simde_vrshrn_n_s32 vrshrn_n_s32 |
| #define simde_vrshrn_n_s64 vrshrn_n_s64 |
| #define simde_vrshrn_n_u16 vrshrn_n_u16 |
| #define simde_vrshrn_n_u32 vrshrn_n_u32 |
| #define simde_vrshrn_n_u64 vrshrn_n_u64 |
| #define simde_vrshrq_n_s16 vrshrq_n_s16 |
| #define simde_vrshrq_n_s32 vrshrq_n_s32 |
| #define simde_vrshrq_n_s64 vrshrq_n_s64 |
| #define simde_vrshrq_n_s8 vrshrq_n_s8 |
| #define simde_vrshrq_n_u16 vrshrq_n_u16 |
| #define simde_vrshrq_n_u32 vrshrq_n_u32 |
| #define simde_vrshrq_n_u64 vrshrq_n_u64 |
| #define simde_vrshrq_n_u8 vrshrq_n_u8 |
| #define simde_vrsqrte_f16 vrsqrte_f16 |
| #define simde_vrsqrte_f32 vrsqrte_f32 |
| #define simde_vrsqrte_f64 vrsqrte_f64 |
| #define simde_vrsqrte_u32 vrsqrte_u32 |
| #define simde_vrsqrted_f64 vrsqrted_f64 |
| #define simde_vrsqrteq_f16 vrsqrteq_f16 |
| #define simde_vrsqrteq_f32 vrsqrteq_f32 |
| #define simde_vrsqrteq_f64 vrsqrteq_f64 |
| #define simde_vrsqrteq_u32 vrsqrteq_u32 |
| #define simde_vrsqrtes_f32 vrsqrtes_f32 |
| #define simde_vrsqrts_f16 vrsqrts_f16 |
| #define simde_vrsqrts_f32 vrsqrts_f32 |
| #define simde_vrsqrts_f64 vrsqrts_f64 |
| #define simde_vrsqrtsd_f64 vrsqrtsd_f64 |
| #define simde_vrsqrtsq_f16 vrsqrtsq_f16 |
| #define simde_vrsqrtsq_f32 vrsqrtsq_f32 |
| #define simde_vrsqrtsq_f64 vrsqrtsq_f64 |
| #define simde_vrsqrtss_f32 vrsqrtss_f32 |
| #define simde_vrsra_n_s16 vrsra_n_s16 |
| #define simde_vrsra_n_s32 vrsra_n_s32 |
| #define simde_vrsra_n_s64 vrsra_n_s64 |
| #define simde_vrsra_n_s8 vrsra_n_s8 |
| #define simde_vrsra_n_u16 vrsra_n_u16 |
| #define simde_vrsra_n_u32 vrsra_n_u32 |
| #define simde_vrsra_n_u64 vrsra_n_u64 |
| #define simde_vrsra_n_u8 vrsra_n_u8 |
| #define simde_vrsrad_n_s64 vrsrad_n_s64 |
| #define simde_vrsrad_n_u64 vrsrad_n_u64 |
| #define simde_vrsraq_n_s16 vrsraq_n_s16 |
| #define simde_vrsraq_n_s32 vrsraq_n_s32 |
| #define simde_vrsraq_n_s64 vrsraq_n_s64 |
| #define simde_vrsraq_n_s8 vrsraq_n_s8 |
| #define simde_vrsraq_n_u16 vrsraq_n_u16 |
| #define simde_vrsraq_n_u32 vrsraq_n_u32 |
| #define simde_vrsraq_n_u64 vrsraq_n_u64 |
| #define simde_vrsraq_n_u8 vrsraq_n_u8 |
| #define simde_vrsubhn_high_s16 vrsubhn_high_s16 |
| #define simde_vrsubhn_high_s32 vrsubhn_high_s32 |
| #define simde_vrsubhn_high_s64 vrsubhn_high_s64 |
| #define simde_vrsubhn_high_u16 vrsubhn_high_u16 |
| #define simde_vrsubhn_high_u32 vrsubhn_high_u32 |
| #define simde_vrsubhn_high_u64 vrsubhn_high_u64 |
| #define simde_vrsubhn_s16 vrsubhn_s16 |
| #define simde_vrsubhn_s32 vrsubhn_s32 |
| #define simde_vrsubhn_s64 vrsubhn_s64 |
| #define simde_vrsubhn_u16 vrsubhn_u16 |
| #define simde_vrsubhn_u32 vrsubhn_u32 |
| #define simde_vrsubhn_u64 vrsubhn_u64 |
| #define simde_vset_lane_bf16 vset_lane_bf16 |
| #define simde_vset_lane_f16 vset_lane_f16 |
| #define simde_vset_lane_f32 vset_lane_f32 |
| #define simde_vset_lane_f64 vset_lane_f64 |
| #define simde_vset_lane_p16 vset_lane_p16 |
| #define simde_vset_lane_p64 vset_lane_p64 |
| #define simde_vset_lane_p8 vset_lane_p8 |
| #define simde_vset_lane_s16 vset_lane_s16 |
| #define simde_vset_lane_s32 vset_lane_s32 |
| #define simde_vset_lane_s64 vset_lane_s64 |
| #define simde_vset_lane_s8 vset_lane_s8 |
| #define simde_vset_lane_u16 vset_lane_u16 |
| #define simde_vset_lane_u32 vset_lane_u32 |
| #define simde_vset_lane_u64 vset_lane_u64 |
| #define simde_vset_lane_u8 vset_lane_u8 |
| #define simde_vsetq_lane_bf16 vsetq_lane_bf16 |
| #define simde_vsetq_lane_f16 vsetq_lane_f16 |
| #define simde_vsetq_lane_f32 vsetq_lane_f32 |
| #define simde_vsetq_lane_f64 vsetq_lane_f64 |
| #define simde_vsetq_lane_p16 vsetq_lane_p16 |
| #define simde_vsetq_lane_p64 vsetq_lane_p64 |
| #define simde_vsetq_lane_p8 vsetq_lane_p8 |
| #define simde_vsetq_lane_s16 vsetq_lane_s16 |
| #define simde_vsetq_lane_s32 vsetq_lane_s32 |
| #define simde_vsetq_lane_s64 vsetq_lane_s64 |
| #define simde_vsetq_lane_s8 vsetq_lane_s8 |
| #define simde_vsetq_lane_u16 vsetq_lane_u16 |
| #define simde_vsetq_lane_u32 vsetq_lane_u32 |
| #define simde_vsetq_lane_u64 vsetq_lane_u64 |
| #define simde_vsetq_lane_u8 vsetq_lane_u8 |
| #define simde_vsha1cq_u32 vsha1cq_u32 |
| #define simde_vsha1h_u32 vsha1h_u32 |
| #define simde_vsha1mq_u32 vsha1mq_u32 |
| #define simde_vsha1pq_u32 vsha1pq_u32 |
| #define simde_vsha1su0q_u32 vsha1su0q_u32 |
| #define simde_vsha1su1q_u32 vsha1su1q_u32 |
| #define simde_vsha256h2q_u32 vsha256h2q_u32 |
| #define simde_vsha256hq_u32 vsha256hq_u32 |
| #define simde_vsha256su0q_u32 vsha256su0q_u32 |
| #define simde_vsha256su1q_u32 vsha256su1q_u32 |
| #define simde_vsha512h2q_u64 vsha512h2q_u64 |
| #define simde_vsha512hq_u64 vsha512hq_u64 |
| #define simde_vsha512su0q_u64 vsha512su0q_u64 |
| #define simde_vsha512su1q_u64 vsha512su1q_u64 |
| #define simde_vshl_n_s16 vshl_n_s16 |
| #define simde_vshl_n_s32 vshl_n_s32 |
| #define simde_vshl_n_s64 vshl_n_s64 |
| #define simde_vshl_n_s8 vshl_n_s8 |
| #define simde_vshl_n_u16 vshl_n_u16 |
| #define simde_vshl_n_u32 vshl_n_u32 |
| #define simde_vshl_n_u64 vshl_n_u64 |
| #define simde_vshl_n_u8 vshl_n_u8 |
| #define simde_vshl_s16 vshl_s16 |
| #define simde_vshl_s32 vshl_s32 |
| #define simde_vshl_s64 vshl_s64 |
| #define simde_vshl_s8 vshl_s8 |
| #define simde_vshl_u16 vshl_u16 |
| #define simde_vshl_u32 vshl_u32 |
| #define simde_vshl_u64 vshl_u64 |
| #define simde_vshl_u8 vshl_u8 |
| #define simde_vshld_n_s64 vshld_n_s64 |
| #define simde_vshld_n_u64 vshld_n_u64 |
| #define simde_vshld_s64 vshld_s64 |
| #define simde_vshld_u64 vshld_u64 |
| #define simde_vshll_high_n_s16 vshll_high_n_s16 |
| #define simde_vshll_high_n_s32 vshll_high_n_s32 |
| #define simde_vshll_high_n_s8 vshll_high_n_s8 |
| #define simde_vshll_high_n_u16 vshll_high_n_u16 |
| #define simde_vshll_high_n_u32 vshll_high_n_u32 |
| #define simde_vshll_high_n_u8 vshll_high_n_u8 |
| #define simde_vshll_n_s16 vshll_n_s16 |
| #define simde_vshll_n_s32 vshll_n_s32 |
| #define simde_vshll_n_s8 vshll_n_s8 |
| #define simde_vshll_n_u16 vshll_n_u16 |
| #define simde_vshll_n_u32 vshll_n_u32 |
| #define simde_vshll_n_u8 vshll_n_u8 |
| #define simde_vshlq_n_s16 vshlq_n_s16 |
| #define simde_vshlq_n_s32 vshlq_n_s32 |
| #define simde_vshlq_n_s64 vshlq_n_s64 |
| #define simde_vshlq_n_s8 vshlq_n_s8 |
| #define simde_vshlq_n_u16 vshlq_n_u16 |
| #define simde_vshlq_n_u32 vshlq_n_u32 |
| #define simde_vshlq_n_u64 vshlq_n_u64 |
| #define simde_vshlq_n_u8 vshlq_n_u8 |
| #define simde_vshlq_s16 vshlq_s16 |
| #define simde_vshlq_s32 vshlq_s32 |
| #define simde_vshlq_s64 vshlq_s64 |
| #define simde_vshlq_s8 vshlq_s8 |
| #define simde_vshlq_u16 vshlq_u16 |
| #define simde_vshlq_u32 vshlq_u32 |
| #define simde_vshlq_u64 vshlq_u64 |
| #define simde_vshlq_u8 vshlq_u8 |
| #define simde_vshr_n_s16 vshr_n_s16 |
| #define simde_vshr_n_s32 vshr_n_s32 |
| #define simde_vshr_n_s64 vshr_n_s64 |
| #define simde_vshr_n_s8 vshr_n_s8 |
| #define simde_vshr_n_u16 vshr_n_u16 |
| #define simde_vshr_n_u32 vshr_n_u32 |
| #define simde_vshr_n_u64 vshr_n_u64 |
| #define simde_vshr_n_u8 vshr_n_u8 |
| #define simde_vshrd_n_s64 vshrd_n_s64 |
| #define simde_vshrd_n_u64 vshrd_n_u64 |
| #define simde_vshrn_high_n_s16 vshrn_high_n_s16 |
| #define simde_vshrn_high_n_s32 vshrn_high_n_s32 |
| #define simde_vshrn_high_n_s64 vshrn_high_n_s64 |
| #define simde_vshrn_high_n_u16 vshrn_high_n_u16 |
| #define simde_vshrn_high_n_u32 vshrn_high_n_u32 |
| #define simde_vshrn_high_n_u64 vshrn_high_n_u64 |
| #define simde_vshrn_n_s16 vshrn_n_s16 |
| #define simde_vshrn_n_s32 vshrn_n_s32 |
| #define simde_vshrn_n_s64 vshrn_n_s64 |
| #define simde_vshrn_n_u16 vshrn_n_u16 |
| #define simde_vshrn_n_u32 vshrn_n_u32 |
| #define simde_vshrn_n_u64 vshrn_n_u64 |
| #define simde_vshrq_n_s16 vshrq_n_s16 |
| #define simde_vshrq_n_s32 vshrq_n_s32 |
| #define simde_vshrq_n_s64 vshrq_n_s64 |
| #define simde_vshrq_n_s8 vshrq_n_s8 |
| #define simde_vshrq_n_u16 vshrq_n_u16 |
| #define simde_vshrq_n_u32 vshrq_n_u32 |
| #define simde_vshrq_n_u64 vshrq_n_u64 |
| #define simde_vshrq_n_u8 vshrq_n_u8 |
| #define simde_vsli_n_p16 vsli_n_p16 |
| #define simde_vsli_n_p64 vsli_n_p64 |
| #define simde_vsli_n_p8 vsli_n_p8 |
| #define simde_vsli_n_s16 vsli_n_s16 |
| #define simde_vsli_n_s32 vsli_n_s32 |
| #define simde_vsli_n_s64 vsli_n_s64 |
| #define simde_vsli_n_s8 vsli_n_s8 |
| #define simde_vsli_n_u16 vsli_n_u16 |
| #define simde_vsli_n_u32 vsli_n_u32 |
| #define simde_vsli_n_u64 vsli_n_u64 |
| #define simde_vsli_n_u8 vsli_n_u8 |
| #define simde_vslid_n_s64 vslid_n_s64 |
| #define simde_vslid_n_u64 vslid_n_u64 |
| #define simde_vsliq_n_p16 vsliq_n_p16 |
| #define simde_vsliq_n_p64 vsliq_n_p64 |
| #define simde_vsliq_n_p8 vsliq_n_p8 |
| #define simde_vsliq_n_s16 vsliq_n_s16 |
| #define simde_vsliq_n_s32 vsliq_n_s32 |
| #define simde_vsliq_n_s64 vsliq_n_s64 |
| #define simde_vsliq_n_s8 vsliq_n_s8 |
| #define simde_vsliq_n_u16 vsliq_n_u16 |
| #define simde_vsliq_n_u32 vsliq_n_u32 |
| #define simde_vsliq_n_u64 vsliq_n_u64 |
| #define simde_vsliq_n_u8 vsliq_n_u8 |
| #define simde_vsm3partw1q_u32 vsm3partw1q_u32 |
| #define simde_vsm3partw2q_u32 vsm3partw2q_u32 |
| #define simde_vsm3ss1q_u32 vsm3ss1q_u32 |
| #define simde_vsm3tt1aq_u32 vsm3tt1aq_u32 |
| #define simde_vsm3tt1bq_u32 vsm3tt1bq_u32 |
| #define simde_vsm3tt2aq_u32 vsm3tt2aq_u32 |
| #define simde_vsm3tt2bq_u32 vsm3tt2bq_u32 |
| #define simde_vsm4ekeyq_u32 vsm4ekeyq_u32 |
| #define simde_vsm4eq_u32 vsm4eq_u32 |
| #define simde_vsqadd_u16 vsqadd_u16 |
| #define simde_vsqadd_u32 vsqadd_u32 |
| #define simde_vsqadd_u64 vsqadd_u64 |
| #define simde_vsqadd_u8 vsqadd_u8 |
| #define simde_vsqaddb_u8 vsqaddb_u8 |
| #define simde_vsqaddd_u64 vsqaddd_u64 |
| #define simde_vsqaddh_u16 vsqaddh_u16 |
| #define simde_vsqaddq_u16 vsqaddq_u16 |
| #define simde_vsqaddq_u32 vsqaddq_u32 |
| #define simde_vsqaddq_u64 vsqaddq_u64 |
| #define simde_vsqaddq_u8 vsqaddq_u8 |
| #define simde_vsqadds_u32 vsqadds_u32 |
| #define simde_vsqrt_f16 vsqrt_f16 |
| #define simde_vsqrt_f32 vsqrt_f32 |
| #define simde_vsqrt_f64 vsqrt_f64 |
| #define simde_vsqrtq_f16 vsqrtq_f16 |
| #define simde_vsqrtq_f32 vsqrtq_f32 |
| #define simde_vsqrtq_f64 vsqrtq_f64 |
| #define simde_vsra_n_s16 vsra_n_s16 |
| #define simde_vsra_n_s32 vsra_n_s32 |
| #define simde_vsra_n_s64 vsra_n_s64 |
| #define simde_vsra_n_s8 vsra_n_s8 |
| #define simde_vsra_n_u16 vsra_n_u16 |
| #define simde_vsra_n_u32 vsra_n_u32 |
| #define simde_vsra_n_u64 vsra_n_u64 |
| #define simde_vsra_n_u8 vsra_n_u8 |
| #define simde_vsrad_n_s64 vsrad_n_s64 |
| #define simde_vsrad_n_u64 vsrad_n_u64 |
| #define simde_vsraq_n_s16 vsraq_n_s16 |
| #define simde_vsraq_n_s32 vsraq_n_s32 |
| #define simde_vsraq_n_s64 vsraq_n_s64 |
| #define simde_vsraq_n_s8 vsraq_n_s8 |
| #define simde_vsraq_n_u16 vsraq_n_u16 |
| #define simde_vsraq_n_u32 vsraq_n_u32 |
| #define simde_vsraq_n_u64 vsraq_n_u64 |
| #define simde_vsraq_n_u8 vsraq_n_u8 |
| #define simde_vsri_n_p16 vsri_n_p16 |
| #define simde_vsri_n_p64 vsri_n_p64 |
| #define simde_vsri_n_p8 vsri_n_p8 |
| #define simde_vsri_n_s16 vsri_n_s16 |
| #define simde_vsri_n_s32 vsri_n_s32 |
| #define simde_vsri_n_s64 vsri_n_s64 |
| #define simde_vsri_n_s8 vsri_n_s8 |
| #define simde_vsri_n_u16 vsri_n_u16 |
| #define simde_vsri_n_u32 vsri_n_u32 |
| #define simde_vsri_n_u64 vsri_n_u64 |
| #define simde_vsri_n_u8 vsri_n_u8 |
| #define simde_vsrid_n_s64 vsrid_n_s64 |
| #define simde_vsrid_n_u64 vsrid_n_u64 |
| #define simde_vsriq_n_p16 vsriq_n_p16 |
| #define simde_vsriq_n_p64 vsriq_n_p64 |
| #define simde_vsriq_n_p8 vsriq_n_p8 |
| #define simde_vsriq_n_s16 vsriq_n_s16 |
| #define simde_vsriq_n_s32 vsriq_n_s32 |
| #define simde_vsriq_n_s64 vsriq_n_s64 |
| #define simde_vsriq_n_s8 vsriq_n_s8 |
| #define simde_vsriq_n_u16 vsriq_n_u16 |
| #define simde_vsriq_n_u32 vsriq_n_u32 |
| #define simde_vsriq_n_u64 vsriq_n_u64 |
| #define simde_vsriq_n_u8 vsriq_n_u8 |
| #define simde_vst1_bf16 vst1_bf16 |
| #define simde_vst1_bf16_x2 vst1_bf16_x2 |
| #define simde_vst1_bf16_x3 vst1_bf16_x3 |
| #define simde_vst1_bf16_x4 vst1_bf16_x4 |
| #define simde_vst1_f16 vst1_f16 |
| #define simde_vst1_f16_x2 vst1_f16_x2 |
| #define simde_vst1_f16_x3 vst1_f16_x3 |
| #define simde_vst1_f16_x4 vst1_f16_x4 |
| #define simde_vst1_f32 vst1_f32 |
| #define simde_vst1_f32_x2 vst1_f32_x2 |
| #define simde_vst1_f32_x3 vst1_f32_x3 |
| #define simde_vst1_f32_x4 vst1_f32_x4 |
| #define simde_vst1_f64 vst1_f64 |
| #define simde_vst1_f64_x2 vst1_f64_x2 |
| #define simde_vst1_f64_x3 vst1_f64_x3 |
| #define simde_vst1_f64_x4 vst1_f64_x4 |
| #define simde_vst1_lane_bf16 vst1_lane_bf16 |
| #define simde_vst1_lane_f16 vst1_lane_f16 |
| #define simde_vst1_lane_f32 vst1_lane_f32 |
| #define simde_vst1_lane_f64 vst1_lane_f64 |
| #define simde_vst1_lane_p16 vst1_lane_p16 |
| #define simde_vst1_lane_p64 vst1_lane_p64 |
| #define simde_vst1_lane_p8 vst1_lane_p8 |
| #define simde_vst1_lane_s16 vst1_lane_s16 |
| #define simde_vst1_lane_s32 vst1_lane_s32 |
| #define simde_vst1_lane_s64 vst1_lane_s64 |
| #define simde_vst1_lane_s8 vst1_lane_s8 |
| #define simde_vst1_lane_u16 vst1_lane_u16 |
| #define simde_vst1_lane_u32 vst1_lane_u32 |
| #define simde_vst1_lane_u64 vst1_lane_u64 |
| #define simde_vst1_lane_u8 vst1_lane_u8 |
| #define simde_vst1_p16 vst1_p16 |
| #define simde_vst1_p16_x2 vst1_p16_x2 |
| #define simde_vst1_p16_x3 vst1_p16_x3 |
| #define simde_vst1_p16_x4 vst1_p16_x4 |
| #define simde_vst1_p64 vst1_p64 |
| #define simde_vst1_p64_x2 vst1_p64_x2 |
| #define simde_vst1_p64_x3 vst1_p64_x3 |
| #define simde_vst1_p64_x4 vst1_p64_x4 |
| #define simde_vst1_p8 vst1_p8 |
| #define simde_vst1_p8_x2 vst1_p8_x2 |
| #define simde_vst1_p8_x3 vst1_p8_x3 |
| #define simde_vst1_p8_x4 vst1_p8_x4 |
| #define simde_vst1_s16 vst1_s16 |
| #define simde_vst1_s16_x2 vst1_s16_x2 |
| #define simde_vst1_s16_x3 vst1_s16_x3 |
| #define simde_vst1_s16_x4 vst1_s16_x4 |
| #define simde_vst1_s32 vst1_s32 |
| #define simde_vst1_s32_x2 vst1_s32_x2 |
| #define simde_vst1_s32_x3 vst1_s32_x3 |
| #define simde_vst1_s32_x4 vst1_s32_x4 |
| #define simde_vst1_s64 vst1_s64 |
| #define simde_vst1_s64_x2 vst1_s64_x2 |
| #define simde_vst1_s64_x3 vst1_s64_x3 |
| #define simde_vst1_s64_x4 vst1_s64_x4 |
| #define simde_vst1_s8 vst1_s8 |
| #define simde_vst1_s8_x2 vst1_s8_x2 |
| #define simde_vst1_s8_x3 vst1_s8_x3 |
| #define simde_vst1_s8_x4 vst1_s8_x4 |
| #define simde_vst1_u16 vst1_u16 |
| #define simde_vst1_u16_x2 vst1_u16_x2 |
| #define simde_vst1_u16_x3 vst1_u16_x3 |
| #define simde_vst1_u16_x4 vst1_u16_x4 |
| #define simde_vst1_u32 vst1_u32 |
| #define simde_vst1_u32_x2 vst1_u32_x2 |
| #define simde_vst1_u32_x3 vst1_u32_x3 |
| #define simde_vst1_u32_x4 vst1_u32_x4 |
| #define simde_vst1_u64 vst1_u64 |
| #define simde_vst1_u64_x2 vst1_u64_x2 |
| #define simde_vst1_u64_x3 vst1_u64_x3 |
| #define simde_vst1_u64_x4 vst1_u64_x4 |
| #define simde_vst1_u8 vst1_u8 |
| #define simde_vst1_u8_x2 vst1_u8_x2 |
| #define simde_vst1_u8_x3 vst1_u8_x3 |
| #define simde_vst1_u8_x4 vst1_u8_x4 |
| #define simde_vst1q_bf16 vst1q_bf16 |
| #define simde_vst1q_bf16_x2 vst1q_bf16_x2 |
| #define simde_vst1q_bf16_x3 vst1q_bf16_x3 |
| #define simde_vst1q_bf16_x4 vst1q_bf16_x4 |
| #define simde_vst1q_f16 vst1q_f16 |
| #define simde_vst1q_f16_x2 vst1q_f16_x2 |
| #define simde_vst1q_f16_x3 vst1q_f16_x3 |
| #define simde_vst1q_f16_x4 vst1q_f16_x4 |
| #define simde_vst1q_f32 vst1q_f32 |
| #define simde_vst1q_f32_x2 vst1q_f32_x2 |
| #define simde_vst1q_f32_x3 vst1q_f32_x3 |
| #define simde_vst1q_f32_x4 vst1q_f32_x4 |
| #define simde_vst1q_f64 vst1q_f64 |
| #define simde_vst1q_f64_x2 vst1q_f64_x2 |
| #define simde_vst1q_f64_x3 vst1q_f64_x3 |
| #define simde_vst1q_f64_x4 vst1q_f64_x4 |
| #define simde_vst1q_lane_bf16 vst1q_lane_bf16 |
| #define simde_vst1q_lane_f16 vst1q_lane_f16 |
| #define simde_vst1q_lane_f32 vst1q_lane_f32 |
| #define simde_vst1q_lane_f64 vst1q_lane_f64 |
| #define simde_vst1q_lane_p16 vst1q_lane_p16 |
| #define simde_vst1q_lane_p64 vst1q_lane_p64 |
| #define simde_vst1q_lane_p8 vst1q_lane_p8 |
| #define simde_vst1q_lane_s16 vst1q_lane_s16 |
| #define simde_vst1q_lane_s32 vst1q_lane_s32 |
| #define simde_vst1q_lane_s64 vst1q_lane_s64 |
| #define simde_vst1q_lane_s8 vst1q_lane_s8 |
| #define simde_vst1q_lane_u16 vst1q_lane_u16 |
| #define simde_vst1q_lane_u32 vst1q_lane_u32 |
| #define simde_vst1q_lane_u64 vst1q_lane_u64 |
| #define simde_vst1q_lane_u8 vst1q_lane_u8 |
| #define simde_vst1q_p16 vst1q_p16 |
| #define simde_vst1q_p16_x2 vst1q_p16_x2 |
| #define simde_vst1q_p16_x3 vst1q_p16_x3 |
| #define simde_vst1q_p16_x4 vst1q_p16_x4 |
| #define simde_vst1q_p64 vst1q_p64 |
| #define simde_vst1q_p64_x2 vst1q_p64_x2 |
| #define simde_vst1q_p64_x3 vst1q_p64_x3 |
| #define simde_vst1q_p64_x4 vst1q_p64_x4 |
| #define simde_vst1q_p8 vst1q_p8 |
| #define simde_vst1q_p8_x2 vst1q_p8_x2 |
| #define simde_vst1q_p8_x3 vst1q_p8_x3 |
| #define simde_vst1q_p8_x4 vst1q_p8_x4 |
| #define simde_vst1q_s16 vst1q_s16 |
| #define simde_vst1q_s16_x2 vst1q_s16_x2 |
| #define simde_vst1q_s16_x3 vst1q_s16_x3 |
| #define simde_vst1q_s16_x4 vst1q_s16_x4 |
| #define simde_vst1q_s32 vst1q_s32 |
| #define simde_vst1q_s32_x2 vst1q_s32_x2 |
| #define simde_vst1q_s32_x3 vst1q_s32_x3 |
| #define simde_vst1q_s32_x4 vst1q_s32_x4 |
| #define simde_vst1q_s64 vst1q_s64 |
| #define simde_vst1q_s64_x2 vst1q_s64_x2 |
| #define simde_vst1q_s64_x3 vst1q_s64_x3 |
| #define simde_vst1q_s64_x4 vst1q_s64_x4 |
| #define simde_vst1q_s8 vst1q_s8 |
| #define simde_vst1q_s8_x2 vst1q_s8_x2 |
| #define simde_vst1q_s8_x3 vst1q_s8_x3 |
| #define simde_vst1q_s8_x4 vst1q_s8_x4 |
| #define simde_vst1q_u16 vst1q_u16 |
| #define simde_vst1q_u16_x2 vst1q_u16_x2 |
| #define simde_vst1q_u16_x3 vst1q_u16_x3 |
| #define simde_vst1q_u16_x4 vst1q_u16_x4 |
| #define simde_vst1q_u32 vst1q_u32 |
| #define simde_vst1q_u32_x2 vst1q_u32_x2 |
| #define simde_vst1q_u32_x3 vst1q_u32_x3 |
| #define simde_vst1q_u32_x4 vst1q_u32_x4 |
| #define simde_vst1q_u64 vst1q_u64 |
| #define simde_vst1q_u64_x2 vst1q_u64_x2 |
| #define simde_vst1q_u64_x3 vst1q_u64_x3 |
| #define simde_vst1q_u64_x4 vst1q_u64_x4 |
| #define simde_vst1q_u8 vst1q_u8 |
| #define simde_vst1q_u8_x2 vst1q_u8_x2 |
| #define simde_vst1q_u8_x3 vst1q_u8_x3 |
| #define simde_vst1q_u8_x4 vst1q_u8_x4 |
| #define simde_vst2_bf16 vst2_bf16 |
| #define simde_vst2_f16 vst2_f16 |
| #define simde_vst2_f32 vst2_f32 |
| #define simde_vst2_f64 vst2_f64 |
| #define simde_vst2_lane_bf16 vst2_lane_bf16 |
| #define simde_vst2_lane_f16 vst2_lane_f16 |
| #define simde_vst2_lane_f32 vst2_lane_f32 |
| #define simde_vst2_lane_f64 vst2_lane_f64 |
| #define simde_vst2_lane_p16 vst2_lane_p16 |
| #define simde_vst2_lane_p64 vst2_lane_p64 |
| #define simde_vst2_lane_p8 vst2_lane_p8 |
| #define simde_vst2_lane_s16 vst2_lane_s16 |
| #define simde_vst2_lane_s32 vst2_lane_s32 |
| #define simde_vst2_lane_s64 vst2_lane_s64 |
| #define simde_vst2_lane_s8 vst2_lane_s8 |
| #define simde_vst2_lane_u16 vst2_lane_u16 |
| #define simde_vst2_lane_u32 vst2_lane_u32 |
| #define simde_vst2_lane_u64 vst2_lane_u64 |
| #define simde_vst2_lane_u8 vst2_lane_u8 |
| #define simde_vst2_p16 vst2_p16 |
| #define simde_vst2_p64 vst2_p64 |
| #define simde_vst2_p8 vst2_p8 |
| #define simde_vst2_s16 vst2_s16 |
| #define simde_vst2_s32 vst2_s32 |
| #define simde_vst2_s64 vst2_s64 |
| #define simde_vst2_s8 vst2_s8 |
| #define simde_vst2_u16 vst2_u16 |
| #define simde_vst2_u32 vst2_u32 |
| #define simde_vst2_u64 vst2_u64 |
| #define simde_vst2_u8 vst2_u8 |
| #define simde_vst2q_bf16 vst2q_bf16 |
| #define simde_vst2q_f16 vst2q_f16 |
| #define simde_vst2q_f32 vst2q_f32 |
| #define simde_vst2q_f64 vst2q_f64 |
| #define simde_vst2q_lane_bf16 vst2q_lane_bf16 |
| #define simde_vst2q_lane_f16 vst2q_lane_f16 |
| #define simde_vst2q_lane_f32 vst2q_lane_f32 |
| #define simde_vst2q_lane_f64 vst2q_lane_f64 |
| #define simde_vst2q_lane_p16 vst2q_lane_p16 |
| #define simde_vst2q_lane_p64 vst2q_lane_p64 |
| #define simde_vst2q_lane_p8 vst2q_lane_p8 |
| #define simde_vst2q_lane_s16 vst2q_lane_s16 |
| #define simde_vst2q_lane_s32 vst2q_lane_s32 |
| #define simde_vst2q_lane_s64 vst2q_lane_s64 |
| #define simde_vst2q_lane_s8 vst2q_lane_s8 |
| #define simde_vst2q_lane_u16 vst2q_lane_u16 |
| #define simde_vst2q_lane_u32 vst2q_lane_u32 |
| #define simde_vst2q_lane_u64 vst2q_lane_u64 |
| #define simde_vst2q_lane_u8 vst2q_lane_u8 |
| #define simde_vst2q_p16 vst2q_p16 |
| #define simde_vst2q_p64 vst2q_p64 |
| #define simde_vst2q_p8 vst2q_p8 |
| #define simde_vst2q_s16 vst2q_s16 |
| #define simde_vst2q_s32 vst2q_s32 |
| #define simde_vst2q_s64 vst2q_s64 |
| #define simde_vst2q_s8 vst2q_s8 |
| #define simde_vst2q_u16 vst2q_u16 |
| #define simde_vst2q_u32 vst2q_u32 |
| #define simde_vst2q_u64 vst2q_u64 |
| #define simde_vst2q_u8 vst2q_u8 |
| #define simde_vst3_bf16 vst3_bf16 |
| #define simde_vst3_f16 vst3_f16 |
| #define simde_vst3_f32 vst3_f32 |
| #define simde_vst3_f64 vst3_f64 |
| #define simde_vst3_lane_bf16 vst3_lane_bf16 |
| #define simde_vst3_lane_f16 vst3_lane_f16 |
| #define simde_vst3_lane_f32 vst3_lane_f32 |
| #define simde_vst3_lane_f64 vst3_lane_f64 |
| #define simde_vst3_lane_p16 vst3_lane_p16 |
| #define simde_vst3_lane_p64 vst3_lane_p64 |
| #define simde_vst3_lane_p8 vst3_lane_p8 |
| #define simde_vst3_lane_s16 vst3_lane_s16 |
| #define simde_vst3_lane_s32 vst3_lane_s32 |
| #define simde_vst3_lane_s64 vst3_lane_s64 |
| #define simde_vst3_lane_s8 vst3_lane_s8 |
| #define simde_vst3_lane_u16 vst3_lane_u16 |
| #define simde_vst3_lane_u32 vst3_lane_u32 |
| #define simde_vst3_lane_u64 vst3_lane_u64 |
| #define simde_vst3_lane_u8 vst3_lane_u8 |
| #define simde_vst3_p16 vst3_p16 |
| #define simde_vst3_p64 vst3_p64 |
| #define simde_vst3_p8 vst3_p8 |
| #define simde_vst3_s16 vst3_s16 |
| #define simde_vst3_s32 vst3_s32 |
| #define simde_vst3_s64 vst3_s64 |
| #define simde_vst3_s8 vst3_s8 |
| #define simde_vst3_u16 vst3_u16 |
| #define simde_vst3_u32 vst3_u32 |
| #define simde_vst3_u64 vst3_u64 |
| #define simde_vst3_u8 vst3_u8 |
| #define simde_vst3q_bf16 vst3q_bf16 |
| #define simde_vst3q_f16 vst3q_f16 |
| #define simde_vst3q_f32 vst3q_f32 |
| #define simde_vst3q_f64 vst3q_f64 |
| #define simde_vst3q_lane_bf16 vst3q_lane_bf16 |
| #define simde_vst3q_lane_f16 vst3q_lane_f16 |
| #define simde_vst3q_lane_f32 vst3q_lane_f32 |
| #define simde_vst3q_lane_f64 vst3q_lane_f64 |
| #define simde_vst3q_lane_p16 vst3q_lane_p16 |
| #define simde_vst3q_lane_p64 vst3q_lane_p64 |
| #define simde_vst3q_lane_p8 vst3q_lane_p8 |
| #define simde_vst3q_lane_s16 vst3q_lane_s16 |
| #define simde_vst3q_lane_s32 vst3q_lane_s32 |
| #define simde_vst3q_lane_s64 vst3q_lane_s64 |
| #define simde_vst3q_lane_s8 vst3q_lane_s8 |
| #define simde_vst3q_lane_u16 vst3q_lane_u16 |
| #define simde_vst3q_lane_u32 vst3q_lane_u32 |
| #define simde_vst3q_lane_u64 vst3q_lane_u64 |
| #define simde_vst3q_lane_u8 vst3q_lane_u8 |
| #define simde_vst3q_p16 vst3q_p16 |
| #define simde_vst3q_p64 vst3q_p64 |
| #define simde_vst3q_p8 vst3q_p8 |
| #define simde_vst3q_s16 vst3q_s16 |
| #define simde_vst3q_s32 vst3q_s32 |
| #define simde_vst3q_s64 vst3q_s64 |
| #define simde_vst3q_s8 vst3q_s8 |
| #define simde_vst3q_u16 vst3q_u16 |
| #define simde_vst3q_u32 vst3q_u32 |
| #define simde_vst3q_u64 vst3q_u64 |
| #define simde_vst3q_u8 vst3q_u8 |
| #define simde_vst4_bf16 vst4_bf16 |
| #define simde_vst4_f16 vst4_f16 |
| #define simde_vst4_f32 vst4_f32 |
| #define simde_vst4_f64 vst4_f64 |
| #define simde_vst4_lane_bf16 vst4_lane_bf16 |
| #define simde_vst4_lane_f16 vst4_lane_f16 |
| #define simde_vst4_lane_f32 vst4_lane_f32 |
| #define simde_vst4_lane_f64 vst4_lane_f64 |
| #define simde_vst4_lane_p16 vst4_lane_p16 |
| #define simde_vst4_lane_p64 vst4_lane_p64 |
| #define simde_vst4_lane_p8 vst4_lane_p8 |
| #define simde_vst4_lane_s16 vst4_lane_s16 |
| #define simde_vst4_lane_s32 vst4_lane_s32 |
| #define simde_vst4_lane_s64 vst4_lane_s64 |
| #define simde_vst4_lane_s8 vst4_lane_s8 |
| #define simde_vst4_lane_u16 vst4_lane_u16 |
| #define simde_vst4_lane_u32 vst4_lane_u32 |
| #define simde_vst4_lane_u64 vst4_lane_u64 |
| #define simde_vst4_lane_u8 vst4_lane_u8 |
| #define simde_vst4_p16 vst4_p16 |
| #define simde_vst4_p64 vst4_p64 |
| #define simde_vst4_p8 vst4_p8 |
| #define simde_vst4_s16 vst4_s16 |
| #define simde_vst4_s32 vst4_s32 |
| #define simde_vst4_s64 vst4_s64 |
| #define simde_vst4_s8 vst4_s8 |
| #define simde_vst4_u16 vst4_u16 |
| #define simde_vst4_u32 vst4_u32 |
| #define simde_vst4_u64 vst4_u64 |
| #define simde_vst4_u8 vst4_u8 |
| #define simde_vst4q_bf16 vst4q_bf16 |
| #define simde_vst4q_f16 vst4q_f16 |
| #define simde_vst4q_f32 vst4q_f32 |
| #define simde_vst4q_f64 vst4q_f64 |
| #define simde_vst4q_lane_bf16 vst4q_lane_bf16 |
| #define simde_vst4q_lane_f16 vst4q_lane_f16 |
| #define simde_vst4q_lane_f32 vst4q_lane_f32 |
| #define simde_vst4q_lane_f64 vst4q_lane_f64 |
| #define simde_vst4q_lane_p16 vst4q_lane_p16 |
| #define simde_vst4q_lane_p64 vst4q_lane_p64 |
| #define simde_vst4q_lane_p8 vst4q_lane_p8 |
| #define simde_vst4q_lane_s16 vst4q_lane_s16 |
| #define simde_vst4q_lane_s32 vst4q_lane_s32 |
| #define simde_vst4q_lane_s64 vst4q_lane_s64 |
| #define simde_vst4q_lane_s8 vst4q_lane_s8 |
| #define simde_vst4q_lane_u16 vst4q_lane_u16 |
| #define simde_vst4q_lane_u32 vst4q_lane_u32 |
| #define simde_vst4q_lane_u64 vst4q_lane_u64 |
| #define simde_vst4q_lane_u8 vst4q_lane_u8 |
| #define simde_vst4q_p16 vst4q_p16 |
| #define simde_vst4q_p64 vst4q_p64 |
| #define simde_vst4q_p8 vst4q_p8 |
| #define simde_vst4q_s16 vst4q_s16 |
| #define simde_vst4q_s32 vst4q_s32 |
| #define simde_vst4q_s64 vst4q_s64 |
| #define simde_vst4q_s8 vst4q_s8 |
| #define simde_vst4q_u16 vst4q_u16 |
| #define simde_vst4q_u32 vst4q_u32 |
| #define simde_vst4q_u64 vst4q_u64 |
| #define simde_vst4q_u8 vst4q_u8 |
| #define simde_vstrq_p128 vstrq_p128 |
| #define simde_vsub_f16 vsub_f16 |
| #define simde_vsub_f32 vsub_f32 |
| #define simde_vsub_f64 vsub_f64 |
| #define simde_vsub_s16 vsub_s16 |
| #define simde_vsub_s32 vsub_s32 |
| #define simde_vsub_s64 vsub_s64 |
| #define simde_vsub_s8 vsub_s8 |
| #define simde_vsub_u16 vsub_u16 |
| #define simde_vsub_u32 vsub_u32 |
| #define simde_vsub_u64 vsub_u64 |
| #define simde_vsub_u8 vsub_u8 |
| #define simde_vsubd_s64 vsubd_s64 |
| #define simde_vsubd_u64 vsubd_u64 |
| #define simde_vsubhn_high_s16 vsubhn_high_s16 |
| #define simde_vsubhn_high_s32 vsubhn_high_s32 |
| #define simde_vsubhn_high_s64 vsubhn_high_s64 |
| #define simde_vsubhn_high_u16 vsubhn_high_u16 |
| #define simde_vsubhn_high_u32 vsubhn_high_u32 |
| #define simde_vsubhn_high_u64 vsubhn_high_u64 |
| #define simde_vsubhn_s16 vsubhn_s16 |
| #define simde_vsubhn_s32 vsubhn_s32 |
| #define simde_vsubhn_s64 vsubhn_s64 |
| #define simde_vsubhn_u16 vsubhn_u16 |
| #define simde_vsubhn_u32 vsubhn_u32 |
| #define simde_vsubhn_u64 vsubhn_u64 |
| #define simde_vsubl_high_s16 vsubl_high_s16 |
| #define simde_vsubl_high_s32 vsubl_high_s32 |
| #define simde_vsubl_high_s8 vsubl_high_s8 |
| #define simde_vsubl_high_u16 vsubl_high_u16 |
| #define simde_vsubl_high_u32 vsubl_high_u32 |
| #define simde_vsubl_high_u8 vsubl_high_u8 |
| #define simde_vsubl_s16 vsubl_s16 |
| #define simde_vsubl_s32 vsubl_s32 |
| #define simde_vsubl_s8 vsubl_s8 |
| #define simde_vsubl_u16 vsubl_u16 |
| #define simde_vsubl_u32 vsubl_u32 |
| #define simde_vsubl_u8 vsubl_u8 |
| #define simde_vsubq_f16 vsubq_f16 |
| #define simde_vsubq_f32 vsubq_f32 |
| #define simde_vsubq_f64 vsubq_f64 |
| #define simde_vsubq_s16 vsubq_s16 |
| #define simde_vsubq_s32 vsubq_s32 |
| #define simde_vsubq_s64 vsubq_s64 |
| #define simde_vsubq_s8 vsubq_s8 |
| #define simde_vsubq_u16 vsubq_u16 |
| #define simde_vsubq_u32 vsubq_u32 |
| #define simde_vsubq_u64 vsubq_u64 |
| #define simde_vsubq_u8 vsubq_u8 |
| #define simde_vsubw_high_s16 vsubw_high_s16 |
| #define simde_vsubw_high_s32 vsubw_high_s32 |
| #define simde_vsubw_high_s8 vsubw_high_s8 |
| #define simde_vsubw_high_u16 vsubw_high_u16 |
| #define simde_vsubw_high_u32 vsubw_high_u32 |
| #define simde_vsubw_high_u8 vsubw_high_u8 |
| #define simde_vsubw_s16 vsubw_s16 |
| #define simde_vsubw_s32 vsubw_s32 |
| #define simde_vsubw_s8 vsubw_s8 |
| #define simde_vsubw_u16 vsubw_u16 |
| #define simde_vsubw_u32 vsubw_u32 |
| #define simde_vsubw_u8 vsubw_u8 |
| #define simde_vsudot_lane_s32 vsudot_lane_s32 |
| #define simde_vsudot_laneq_s32 vsudot_laneq_s32 |
| #define simde_vsudotq_lane_s32 vsudotq_lane_s32 |
| #define simde_vsudotq_laneq_s32 vsudotq_laneq_s32 |
| #define simde_vtbl1_p8 vtbl1_p8 |
| #define simde_vtbl1_s8 vtbl1_s8 |
| #define simde_vtbl1_u8 vtbl1_u8 |
| #define simde_vtbl2_p8 vtbl2_p8 |
| #define simde_vtbl2_s8 vtbl2_s8 |
| #define simde_vtbl2_u8 vtbl2_u8 |
| #define simde_vtbl3_p8 vtbl3_p8 |
| #define simde_vtbl3_s8 vtbl3_s8 |
| #define simde_vtbl3_u8 vtbl3_u8 |
| #define simde_vtbl4_p8 vtbl4_p8 |
| #define simde_vtbl4_s8 vtbl4_s8 |
| #define simde_vtbl4_u8 vtbl4_u8 |
| #define simde_vtbx1_p8 vtbx1_p8 |
| #define simde_vtbx1_s8 vtbx1_s8 |
| #define simde_vtbx1_u8 vtbx1_u8 |
| #define simde_vtbx2_p8 vtbx2_p8 |
| #define simde_vtbx2_s8 vtbx2_s8 |
| #define simde_vtbx2_u8 vtbx2_u8 |
| #define simde_vtbx3_p8 vtbx3_p8 |
| #define simde_vtbx3_s8 vtbx3_s8 |
| #define simde_vtbx3_u8 vtbx3_u8 |
| #define simde_vtbx4_p8 vtbx4_p8 |
| #define simde_vtbx4_s8 vtbx4_s8 |
| #define simde_vtbx4_u8 vtbx4_u8 |
| #define simde_vtrn_f16 vtrn_f16 |
| #define simde_vtrn_f32 vtrn_f32 |
| #define simde_vtrn_p16 vtrn_p16 |
| #define simde_vtrn_p8 vtrn_p8 |
| #define simde_vtrn_s16 vtrn_s16 |
| #define simde_vtrn_s32 vtrn_s32 |
| #define simde_vtrn_s8 vtrn_s8 |
| #define simde_vtrn_u16 vtrn_u16 |
| #define simde_vtrn_u32 vtrn_u32 |
| #define simde_vtrn_u8 vtrn_u8 |
| #define simde_vtrn1_f16 vtrn1_f16 |
| #define simde_vtrn1_f32 vtrn1_f32 |
| #define simde_vtrn1_p16 vtrn1_p16 |
| #define simde_vtrn1_p8 vtrn1_p8 |
| #define simde_vtrn1_s16 vtrn1_s16 |
| #define simde_vtrn1_s32 vtrn1_s32 |
| #define simde_vtrn1_s8 vtrn1_s8 |
| #define simde_vtrn1_u16 vtrn1_u16 |
| #define simde_vtrn1_u32 vtrn1_u32 |
| #define simde_vtrn1_u8 vtrn1_u8 |
| #define simde_vtrn1q_f16 vtrn1q_f16 |
| #define simde_vtrn1q_f32 vtrn1q_f32 |
| #define simde_vtrn1q_f64 vtrn1q_f64 |
| #define simde_vtrn1q_p16 vtrn1q_p16 |
| #define simde_vtrn1q_p64 vtrn1q_p64 |
| #define simde_vtrn1q_p8 vtrn1q_p8 |
| #define simde_vtrn1q_s16 vtrn1q_s16 |
| #define simde_vtrn1q_s32 vtrn1q_s32 |
| #define simde_vtrn1q_s64 vtrn1q_s64 |
| #define simde_vtrn1q_s8 vtrn1q_s8 |
| #define simde_vtrn1q_u16 vtrn1q_u16 |
| #define simde_vtrn1q_u32 vtrn1q_u32 |
| #define simde_vtrn1q_u64 vtrn1q_u64 |
| #define simde_vtrn1q_u8 vtrn1q_u8 |
| #define simde_vtrn2_f16 vtrn2_f16 |
| #define simde_vtrn2_f32 vtrn2_f32 |
| #define simde_vtrn2_p16 vtrn2_p16 |
| #define simde_vtrn2_p8 vtrn2_p8 |
| #define simde_vtrn2_s16 vtrn2_s16 |
| #define simde_vtrn2_s32 vtrn2_s32 |
| #define simde_vtrn2_s8 vtrn2_s8 |
| #define simde_vtrn2_u16 vtrn2_u16 |
| #define simde_vtrn2_u32 vtrn2_u32 |
| #define simde_vtrn2_u8 vtrn2_u8 |
| #define simde_vtrn2q_f16 vtrn2q_f16 |
| #define simde_vtrn2q_f32 vtrn2q_f32 |
| #define simde_vtrn2q_f64 vtrn2q_f64 |
| #define simde_vtrn2q_p16 vtrn2q_p16 |
| #define simde_vtrn2q_p64 vtrn2q_p64 |
| #define simde_vtrn2q_p8 vtrn2q_p8 |
| #define simde_vtrn2q_s16 vtrn2q_s16 |
| #define simde_vtrn2q_s32 vtrn2q_s32 |
| #define simde_vtrn2q_s64 vtrn2q_s64 |
| #define simde_vtrn2q_s8 vtrn2q_s8 |
| #define simde_vtrn2q_u16 vtrn2q_u16 |
| #define simde_vtrn2q_u32 vtrn2q_u32 |
| #define simde_vtrn2q_u64 vtrn2q_u64 |
| #define simde_vtrn2q_u8 vtrn2q_u8 |
| #define simde_vtrnq_f16 vtrnq_f16 |
| #define simde_vtrnq_f32 vtrnq_f32 |
| #define simde_vtrnq_p16 vtrnq_p16 |
| #define simde_vtrnq_p8 vtrnq_p8 |
| #define simde_vtrnq_s16 vtrnq_s16 |
| #define simde_vtrnq_s32 vtrnq_s32 |
| #define simde_vtrnq_s8 vtrnq_s8 |
| #define simde_vtrnq_u16 vtrnq_u16 |
| #define simde_vtrnq_u32 vtrnq_u32 |
| #define simde_vtrnq_u8 vtrnq_u8 |
| #define simde_vtst_p64 vtst_p64 |
| #define simde_vtst_p8 vtst_p8 |
| #define simde_vtst_s16 vtst_s16 |
| #define simde_vtst_s32 vtst_s32 |
| #define simde_vtst_s64 vtst_s64 |
| #define simde_vtst_s8 vtst_s8 |
| #define simde_vtst_u16 vtst_u16 |
| #define simde_vtst_u32 vtst_u32 |
| #define simde_vtst_u64 vtst_u64 |
| #define simde_vtst_u8 vtst_u8 |
| #define simde_vtstd_s64 vtstd_s64 |
| #define simde_vtstd_u64 vtstd_u64 |
| #define simde_vtstq_p64 vtstq_p64 |
| #define simde_vtstq_p8 vtstq_p8 |
| #define simde_vtstq_s16 vtstq_s16 |
| #define simde_vtstq_s32 vtstq_s32 |
| #define simde_vtstq_s64 vtstq_s64 |
| #define simde_vtstq_s8 vtstq_s8 |
| #define simde_vtstq_u16 vtstq_u16 |
| #define simde_vtstq_u32 vtstq_u32 |
| #define simde_vtstq_u64 vtstq_u64 |
| #define simde_vtstq_u8 vtstq_u8 |
| #define simde_vuqadd_s16 vuqadd_s16 |
| #define simde_vuqadd_s32 vuqadd_s32 |
| #define simde_vuqadd_s64 vuqadd_s64 |
| #define simde_vuqadd_s8 vuqadd_s8 |
| #define simde_vuqaddb_s8 vuqaddb_s8 |
| #define simde_vuqaddd_s64 vuqaddd_s64 |
| #define simde_vuqaddh_s16 vuqaddh_s16 |
| #define simde_vuqaddq_s16 vuqaddq_s16 |
| #define simde_vuqaddq_s32 vuqaddq_s32 |
| #define simde_vuqaddq_s64 vuqaddq_s64 |
| #define simde_vuqaddq_s8 vuqaddq_s8 |
| #define simde_vuqadds_s32 vuqadds_s32 |
| #define simde_vusdot_lane_s32 vusdot_lane_s32 |
| #define simde_vusdot_laneq_s32 vusdot_laneq_s32 |
| #define simde_vusdot_s32 vusdot_s32 |
| #define simde_vusdotq_lane_s32 vusdotq_lane_s32 |
| #define simde_vusdotq_laneq_s32 vusdotq_laneq_s32 |
| #define simde_vusdotq_s32 vusdotq_s32 |
| #define simde_vusmmlaq_s32 vusmmlaq_s32 |
| #define simde_vuzp_f16 vuzp_f16 |
| #define simde_vuzp_f32 vuzp_f32 |
| #define simde_vuzp_p16 vuzp_p16 |
| #define simde_vuzp_p8 vuzp_p8 |
| #define simde_vuzp_s16 vuzp_s16 |
| #define simde_vuzp_s32 vuzp_s32 |
| #define simde_vuzp_s8 vuzp_s8 |
| #define simde_vuzp_u16 vuzp_u16 |
| #define simde_vuzp_u32 vuzp_u32 |
| #define simde_vuzp_u8 vuzp_u8 |
| #define simde_vuzp1_f16 vuzp1_f16 |
| #define simde_vuzp1_f32 vuzp1_f32 |
| #define simde_vuzp1_p16 vuzp1_p16 |
| #define simde_vuzp1_p8 vuzp1_p8 |
| #define simde_vuzp1_s16 vuzp1_s16 |
| #define simde_vuzp1_s32 vuzp1_s32 |
| #define simde_vuzp1_s8 vuzp1_s8 |
| #define simde_vuzp1_u16 vuzp1_u16 |
| #define simde_vuzp1_u32 vuzp1_u32 |
| #define simde_vuzp1_u8 vuzp1_u8 |
| #define simde_vuzp1q_f16 vuzp1q_f16 |
| #define simde_vuzp1q_f32 vuzp1q_f32 |
| #define simde_vuzp1q_f64 vuzp1q_f64 |
| #define simde_vuzp1q_p16 vuzp1q_p16 |
| #define simde_vuzp1q_p64 vuzp1q_p64 |
| #define simde_vuzp1q_p8 vuzp1q_p8 |
| #define simde_vuzp1q_s16 vuzp1q_s16 |
| #define simde_vuzp1q_s32 vuzp1q_s32 |
| #define simde_vuzp1q_s64 vuzp1q_s64 |
| #define simde_vuzp1q_s8 vuzp1q_s8 |
| #define simde_vuzp1q_u16 vuzp1q_u16 |
| #define simde_vuzp1q_u32 vuzp1q_u32 |
| #define simde_vuzp1q_u64 vuzp1q_u64 |
| #define simde_vuzp1q_u8 vuzp1q_u8 |
| #define simde_vuzp2_f16 vuzp2_f16 |
| #define simde_vuzp2_f32 vuzp2_f32 |
| #define simde_vuzp2_p16 vuzp2_p16 |
| #define simde_vuzp2_p8 vuzp2_p8 |
| #define simde_vuzp2_s16 vuzp2_s16 |
| #define simde_vuzp2_s32 vuzp2_s32 |
| #define simde_vuzp2_s8 vuzp2_s8 |
| #define simde_vuzp2_u16 vuzp2_u16 |
| #define simde_vuzp2_u32 vuzp2_u32 |
| #define simde_vuzp2_u8 vuzp2_u8 |
| #define simde_vuzp2q_f16 vuzp2q_f16 |
| #define simde_vuzp2q_f32 vuzp2q_f32 |
| #define simde_vuzp2q_f64 vuzp2q_f64 |
| #define simde_vuzp2q_p16 vuzp2q_p16 |
| #define simde_vuzp2q_p64 vuzp2q_p64 |
| #define simde_vuzp2q_p8 vuzp2q_p8 |
| #define simde_vuzp2q_s16 vuzp2q_s16 |
| #define simde_vuzp2q_s32 vuzp2q_s32 |
| #define simde_vuzp2q_s64 vuzp2q_s64 |
| #define simde_vuzp2q_s8 vuzp2q_s8 |
| #define simde_vuzp2q_u16 vuzp2q_u16 |
| #define simde_vuzp2q_u32 vuzp2q_u32 |
| #define simde_vuzp2q_u64 vuzp2q_u64 |
| #define simde_vuzp2q_u8 vuzp2q_u8 |
| #define simde_vuzpq_f16 vuzpq_f16 |
| #define simde_vuzpq_f32 vuzpq_f32 |
| #define simde_vuzpq_p16 vuzpq_p16 |
| #define simde_vuzpq_p8 vuzpq_p8 |
| #define simde_vuzpq_s16 vuzpq_s16 |
| #define simde_vuzpq_s32 vuzpq_s32 |
| #define simde_vuzpq_s8 vuzpq_s8 |
| #define simde_vuzpq_u16 vuzpq_u16 |
| #define simde_vuzpq_u32 vuzpq_u32 |
| #define simde_vuzpq_u8 vuzpq_u8 |
| #define simde_vxarq_u64 vxarq_u64 |
| #define simde_vzip_f16 vzip_f16 |
| #define simde_vzip_f32 vzip_f32 |
| #define simde_vzip_p16 vzip_p16 |
| #define simde_vzip_p8 vzip_p8 |
| #define simde_vzip_s16 vzip_s16 |
| #define simde_vzip_s32 vzip_s32 |
| #define simde_vzip_s8 vzip_s8 |
| #define simde_vzip_u16 vzip_u16 |
| #define simde_vzip_u32 vzip_u32 |
| #define simde_vzip_u8 vzip_u8 |
| #define simde_vzip1_f16 vzip1_f16 |
| #define simde_vzip1_f32 vzip1_f32 |
| #define simde_vzip1_p16 vzip1_p16 |
| #define simde_vzip1_p8 vzip1_p8 |
| #define simde_vzip1_s16 vzip1_s16 |
| #define simde_vzip1_s32 vzip1_s32 |
| #define simde_vzip1_s8 vzip1_s8 |
| #define simde_vzip1_u16 vzip1_u16 |
| #define simde_vzip1_u32 vzip1_u32 |
| #define simde_vzip1_u8 vzip1_u8 |
| #define simde_vzip1q_f16 vzip1q_f16 |
| #define simde_vzip1q_f32 vzip1q_f32 |
| #define simde_vzip1q_f64 vzip1q_f64 |
| #define simde_vzip1q_p16 vzip1q_p16 |
| #define simde_vzip1q_p64 vzip1q_p64 |
| #define simde_vzip1q_p8 vzip1q_p8 |
| #define simde_vzip1q_s16 vzip1q_s16 |
| #define simde_vzip1q_s32 vzip1q_s32 |
| #define simde_vzip1q_s64 vzip1q_s64 |
| #define simde_vzip1q_s8 vzip1q_s8 |
| #define simde_vzip1q_u16 vzip1q_u16 |
| #define simde_vzip1q_u32 vzip1q_u32 |
| #define simde_vzip1q_u64 vzip1q_u64 |
| #define simde_vzip1q_u8 vzip1q_u8 |
| #define simde_vzip2_f16 vzip2_f16 |
| #define simde_vzip2_f32 vzip2_f32 |
| #define simde_vzip2_p16 vzip2_p16 |
| #define simde_vzip2_p8 vzip2_p8 |
| #define simde_vzip2_s16 vzip2_s16 |
| #define simde_vzip2_s32 vzip2_s32 |
| #define simde_vzip2_s8 vzip2_s8 |
| #define simde_vzip2_u16 vzip2_u16 |
| #define simde_vzip2_u32 vzip2_u32 |
| #define simde_vzip2_u8 vzip2_u8 |
| #define simde_vzip2q_f16 vzip2q_f16 |
| #define simde_vzip2q_f32 vzip2q_f32 |
| #define simde_vzip2q_f64 vzip2q_f64 |
| #define simde_vzip2q_p16 vzip2q_p16 |
| #define simde_vzip2q_p64 vzip2q_p64 |
| #define simde_vzip2q_p8 vzip2q_p8 |
| #define simde_vzip2q_s16 vzip2q_s16 |
| #define simde_vzip2q_s32 vzip2q_s32 |
| #define simde_vzip2q_s64 vzip2q_s64 |
| #define simde_vzip2q_s8 vzip2q_s8 |
| #define simde_vzip2q_u16 vzip2q_u16 |
| #define simde_vzip2q_u32 vzip2q_u32 |
| #define simde_vzip2q_u64 vzip2q_u64 |
| #define simde_vzip2q_u8 vzip2q_u8 |
| #define simde_vzipq_f16 vzipq_f16 |
| #define simde_vzipq_f32 vzipq_f32 |
| #define simde_vzipq_p16 vzipq_p16 |
| #define simde_vzipq_p8 vzipq_p8 |
| #define simde_vzipq_s16 vzipq_s16 |
| #define simde_vzipq_s32 vzipq_s32 |
| #define simde_vzipq_s8 vzipq_s8 |
| #define simde_vzipq_u16 vzipq_u16 |
| #define simde_vzipq_u32 vzipq_u32 |
| #define simde_vzipq_u8 vzipq_u8 |
| |
| ALWAYS_INLINE void simde_mm_pause() |
| { |
| asm volatile("isb\n"); |
| } |
| |
| #else // !(CPU(ARM64) && OS(DARWIN)) |
| |
| #if !CPU(ARM64) |
| #ifndef SIMDE_ARM_NEON_A32V8_NO_NATIVE |
| #define SIMDE_ARM_NEON_A32V8_NO_NATIVE 1 |
| #endif |
| #endif |
| |
| // Workaround: neon.h contains MSVC-specific workarounds guarded by _MSC_VER < 1938 |
| // that use intrinsics not available in clang-cl. Temporarily set _MSC_VER >= 1938 |
| // to skip those workarounds when building with clang-cl. |
| // https://developercommunity.visualstudio.com/t/In-arm64_neonh-vsqaddb_u8-vsqaddh_u16/10271747 |
| #if defined(_MSC_VER) && defined(__clang__) |
| #pragma push_macro("_MSC_VER") |
| #undef _MSC_VER |
| #define _MSC_VER 1938 |
| #endif |
| |
| IGNORE_WARNINGS_BEGIN("constant-conversion") |
| IGNORE_WARNINGS_BEGIN("uninitialized") |
| #include <wtf/simde/arm/neon.h> |
| #include <wtf/simde/arm/sve.h> |
| IGNORE_WARNINGS_END |
| IGNORE_WARNINGS_END |
| |
| #if defined(_MSC_VER) && defined(__clang__) |
| #pragma pop_macro("_MSC_VER") |
| #endif |
| |
| #endif // CPU(ARM64) && OS(DARWIN) |
