test/spec/relaxed-atomics.wast

;; Generated by scripts/test/generate-atomic-spec-test.py. Do not edit manually.

(module
  (memory i32 1 1)
  (memory i64 1 1)

  ;; Memory index must come before memory ordering if present.
  ;; Both immediates are optional; an ommitted memory ordering will be treated as seqcst.
  (func $test-all-ops
    (drop (i32.atomic.load (i32.const 0)))
    (drop (i32.atomic.load acqrel (i32.const 0)))
    (drop (i32.atomic.load seqcst (i32.const 0)))
    (drop (i32.atomic.load 0 (i32.const 0)))
    (drop (i32.atomic.load 0 acqrel (i32.const 0)))
    (drop (i32.atomic.load 0 seqcst (i32.const 0)))
    (drop (i32.atomic.load 1 (i64.const 0)))
    (drop (i32.atomic.load 1 acqrel (i64.const 0)))
    (drop (i32.atomic.load 1 seqcst (i64.const 0)))
    (drop (i64.atomic.load (i32.const 0)))
    (drop (i64.atomic.load acqrel (i32.const 0)))
    (drop (i64.atomic.load seqcst (i32.const 0)))
    (drop (i64.atomic.load 0 (i32.const 0)))
    (drop (i64.atomic.load 0 acqrel (i32.const 0)))
    (drop (i64.atomic.load 0 seqcst (i32.const 0)))
    (drop (i64.atomic.load 1 (i64.const 0)))
    (drop (i64.atomic.load 1 acqrel (i64.const 0)))
    (drop (i64.atomic.load 1 seqcst (i64.const 0)))
    (drop (i32.atomic.load8_u (i32.const 0)))
    (drop (i32.atomic.load8_u acqrel (i32.const 0)))
    (drop (i32.atomic.load8_u seqcst (i32.const 0)))
    (drop (i32.atomic.load8_u 0 (i32.const 0)))
    (drop (i32.atomic.load8_u 0 acqrel (i32.const 0)))
    (drop (i32.atomic.load8_u 0 seqcst (i32.const 0)))
    (drop (i32.atomic.load8_u 1 (i64.const 0)))
    (drop (i32.atomic.load8_u 1 acqrel (i64.const 0)))
    (drop (i32.atomic.load8_u 1 seqcst (i64.const 0)))
    (drop (i32.atomic.load16_u (i32.const 0)))
    (drop (i32.atomic.load16_u acqrel (i32.const 0)))
    (drop (i32.atomic.load16_u seqcst (i32.const 0)))
    (drop (i32.atomic.load16_u 0 (i32.const 0)))
    (drop (i32.atomic.load16_u 0 acqrel (i32.const 0)))
    (drop (i32.atomic.load16_u 0 seqcst (i32.const 0)))
    (drop (i32.atomic.load16_u 1 (i64.const 0)))
    (drop (i32.atomic.load16_u 1 acqrel (i64.const 0)))
    (drop (i32.atomic.load16_u 1 seqcst (i64.const 0)))
    (drop (i64.atomic.load8_u (i32.const 0)))
    (drop (i64.atomic.load8_u acqrel (i32.const 0)))
    (drop (i64.atomic.load8_u seqcst (i32.const 0)))
    (drop (i64.atomic.load8_u 0 (i32.const 0)))
    (drop (i64.atomic.load8_u 0 acqrel (i32.const 0)))
    (drop (i64.atomic.load8_u 0 seqcst (i32.const 0)))
    (drop (i64.atomic.load8_u 1 (i64.const 0)))
    (drop (i64.atomic.load8_u 1 acqrel (i64.const 0)))
    (drop (i64.atomic.load8_u 1 seqcst (i64.const 0)))
    (drop (i64.atomic.load16_u (i32.const 0)))
    (drop (i64.atomic.load16_u acqrel (i32.const 0)))
    (drop (i64.atomic.load16_u seqcst (i32.const 0)))
    (drop (i64.atomic.load16_u 0 (i32.const 0)))
    (drop (i64.atomic.load16_u 0 acqrel (i32.const 0)))
    (drop (i64.atomic.load16_u 0 seqcst (i32.const 0)))
    (drop (i64.atomic.load16_u 1 (i64.const 0)))
    (drop (i64.atomic.load16_u 1 acqrel (i64.const 0)))
    (drop (i64.atomic.load16_u 1 seqcst (i64.const 0)))
    (drop (i64.atomic.load32_u (i32.const 0)))
    (drop (i64.atomic.load32_u acqrel (i32.const 0)))
    (drop (i64.atomic.load32_u seqcst (i32.const 0)))
    (drop (i64.atomic.load32_u 0 (i32.const 0)))
    (drop (i64.atomic.load32_u 0 acqrel (i32.const 0)))
    (drop (i64.atomic.load32_u 0 seqcst (i32.const 0)))
    (drop (i64.atomic.load32_u 1 (i64.const 0)))
    (drop (i64.atomic.load32_u 1 acqrel (i64.const 0)))
    (drop (i64.atomic.load32_u 1 seqcst (i64.const 0)))
    (i32.atomic.store (i32.const 0) (i32.const 42))
    (i32.atomic.store acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store 0 (i32.const 0) (i32.const 42))
    (i32.atomic.store 0 acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store 0 seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store 1 (i64.const 0) (i32.const 42))
    (i32.atomic.store 1 acqrel (i64.const 0) (i32.const 42))
    (i32.atomic.store 1 seqcst (i64.const 0) (i32.const 42))
    (i64.atomic.store (i32.const 0) (i64.const 42))
    (i64.atomic.store acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store 0 (i32.const 0) (i64.const 42))
    (i64.atomic.store 0 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store 0 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store 1 (i64.const 0) (i64.const 42))
    (i64.atomic.store 1 acqrel (i64.const 0) (i64.const 42))
    (i64.atomic.store 1 seqcst (i64.const 0) (i64.const 42))
    (i32.atomic.store8 (i32.const 0) (i32.const 42))
    (i32.atomic.store8 acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store8 seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store8 0 (i32.const 0) (i32.const 42))
    (i32.atomic.store8 0 acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store8 0 seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store8 1 (i64.const 0) (i32.const 42))
    (i32.atomic.store8 1 acqrel (i64.const 0) (i32.const 42))
    (i32.atomic.store8 1 seqcst (i64.const 0) (i32.const 42))
    (i32.atomic.store16 (i32.const 0) (i32.const 42))
    (i32.atomic.store16 acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store16 seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store16 0 (i32.const 0) (i32.const 42))
    (i32.atomic.store16 0 acqrel (i32.const 0) (i32.const 42))
    (i32.atomic.store16 0 seqcst (i32.const 0) (i32.const 42))
    (i32.atomic.store16 1 (i64.const 0) (i32.const 42))
    (i32.atomic.store16 1 acqrel (i64.const 0) (i32.const 42))
    (i32.atomic.store16 1 seqcst (i64.const 0) (i32.const 42))
    (i64.atomic.store8 (i32.const 0) (i64.const 42))
    (i64.atomic.store8 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store8 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store8 0 (i32.const 0) (i64.const 42))
    (i64.atomic.store8 0 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store8 0 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store8 1 (i64.const 0) (i64.const 42))
    (i64.atomic.store8 1 acqrel (i64.const 0) (i64.const 42))
    (i64.atomic.store8 1 seqcst (i64.const 0) (i64.const 42))
    (i64.atomic.store16 (i32.const 0) (i64.const 42))
    (i64.atomic.store16 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store16 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store16 0 (i32.const 0) (i64.const 42))
    (i64.atomic.store16 0 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store16 0 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store16 1 (i64.const 0) (i64.const 42))
    (i64.atomic.store16 1 acqrel (i64.const 0) (i64.const 42))
    (i64.atomic.store16 1 seqcst (i64.const 0) (i64.const 42))
    (i64.atomic.store32 (i32.const 0) (i64.const 42))
    (i64.atomic.store32 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store32 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store32 0 (i32.const 0) (i64.const 42))
    (i64.atomic.store32 0 acqrel (i32.const 0) (i64.const 42))
    (i64.atomic.store32 0 seqcst (i32.const 0) (i64.const 42))
    (i64.atomic.store32 1 (i64.const 0) (i64.const 42))
    (i64.atomic.store32 1 acqrel (i64.const 0) (i64.const 42))
    (i64.atomic.store32 1 seqcst (i64.const 0) (i64.const 42))
    (drop (i32.atomic.rmw.add (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.add 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.add (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.add 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.add_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.add_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.add_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.add_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.add_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.add_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.add_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.sub (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.sub 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.sub (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.sub 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.sub_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.sub_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.sub_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.sub_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.sub_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.sub_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.sub_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.and (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.and 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.and (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.and 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.and_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.and_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.and_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.and_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.and_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.and_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.and_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.or (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.or 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.or (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.or 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.or_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.or_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.or_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.or_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.or_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.or_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.or_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.xor (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xor 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.xor (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xor 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.xor_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xor_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xor_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.xor_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xor_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xor_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xor_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.xchg (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw.xchg 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw.xchg (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw.xchg 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw8.xchg_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw8.xchg_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 0 (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 0 acqrel (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 0 seqcst (i32.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 1 (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 1 acqrel (i64.const 0) (i32.const 42)))
    (drop (i32.atomic.rmw16.xchg_u 1 seqcst (i64.const 0) (i32.const 42)))
    (drop (i64.atomic.rmw8.xchg_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw8.xchg_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw16.xchg_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 0 (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 0 acqrel (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 0 seqcst (i32.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 1 (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 1 acqrel (i64.const 0) (i64.const 42)))
    (drop (i64.atomic.rmw32.xchg_u 1 seqcst (i64.const 0) (i64.const 42)))
    (drop (i32.atomic.rmw.cmpxchg (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 0 (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 0 acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 0 seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 1 (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 1 acqrel (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw.cmpxchg 1 seqcst (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i64.atomic.rmw.cmpxchg (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 0 (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 0 acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 0 seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 1 (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 1 acqrel (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw.cmpxchg 1 seqcst (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 0 (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 0 acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 0 seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 1 (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 1 acqrel (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw8.cmpxchg_u 1 seqcst (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 0 (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 0 acqrel (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 0 seqcst (i32.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 1 (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 1 acqrel (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i32.atomic.rmw16.cmpxchg_u 1 seqcst (i64.const 0) (i32.const 42) (i32.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 0 (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 0 acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 0 seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 1 (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 1 acqrel (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw8.cmpxchg_u 1 seqcst (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 0 (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 0 acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 0 seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 1 (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 1 acqrel (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw16.cmpxchg_u 1 seqcst (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 0 (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 0 acqrel (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 0 seqcst (i32.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 1 (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 1 acqrel (i64.const 0) (i64.const 42) (i64.const 42)))
    (drop (i64.atomic.rmw32.cmpxchg_u 1 seqcst (i64.const 0) (i64.const 42) (i64.const 42)))
  )
)

(assert_invalid (module
  (memory 1 1 shared)

  (func $i32load (drop (i32.load acqrel (i32.const 51))))
) "Can't set memory ordering for non-atomic i32.load")

(module binary
  "\00asm\01\00\00\00" ;; Wasm header
  "\01\04\01" ;; Type section
    "\60\00\00" ;; $test-all-ops type
  "\03\02\01\00" ;; Function section
  "\05\07\02" ;; Memory section
    "\01\01\01" ;; (memory i32 1 1)
    "\05\01\01" ;; (memory i64 1 1)
  "\0a\a9\2d\01" ;; Code section
  "\a6\2d\00" ;; func $test-all-ops

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\10" ;; i32.atomic.load
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\10" ;; i32.atomic.load
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\10" ;; i32.atomic.load
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\10" ;; i32.atomic.load
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\11" ;; i64.atomic.load
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\11" ;; i64.atomic.load
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\11" ;; i64.atomic.load
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\11" ;; i64.atomic.load
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\12" ;; i32.atomic.load8_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\13" ;; i32.atomic.load16_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\14" ;; i64.atomic.load8_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\15" ;; i64.atomic.load16_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\fe\16" ;; i64.atomic.load32_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\17" ;; i32.atomic.store
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\18" ;; i64.atomic.store
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\19" ;; i32.atomic.store8
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1a" ;; i32.atomic.store16
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1b" ;; i64.atomic.store8
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1c" ;; i64.atomic.store16
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\02" ;; Alignment of 2
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\01" ;; acqrel memory ordering
    "\00" ;; offset

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1d" ;; i64.atomic.store32
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\1e" ;; i32.atomic.rmw.add
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\1f" ;; i64.atomic.rmw.add
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\20" ;; i32.atomic.rmw8.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\21" ;; i32.atomic.rmw16.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\22" ;; i64.atomic.rmw8.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\23" ;; i64.atomic.rmw16.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\24" ;; i64.atomic.rmw32.add_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\25" ;; i32.atomic.rmw.sub
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\26" ;; i64.atomic.rmw.sub
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\27" ;; i32.atomic.rmw8.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\28" ;; i32.atomic.rmw16.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\29" ;; i64.atomic.rmw8.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2a" ;; i64.atomic.rmw16.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2b" ;; i64.atomic.rmw32.sub_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2c" ;; i32.atomic.rmw.and
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\2d" ;; i64.atomic.rmw.and
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2e" ;; i32.atomic.rmw8.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\2f" ;; i32.atomic.rmw16.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\30" ;; i64.atomic.rmw8.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\31" ;; i64.atomic.rmw16.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\32" ;; i64.atomic.rmw32.and_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\33" ;; i32.atomic.rmw.or
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\34" ;; i64.atomic.rmw.or
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\35" ;; i32.atomic.rmw8.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\36" ;; i32.atomic.rmw16.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\37" ;; i64.atomic.rmw8.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\38" ;; i64.atomic.rmw16.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\39" ;; i64.atomic.rmw32.or_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3a" ;; i32.atomic.rmw.xor
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3b" ;; i64.atomic.rmw.xor
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3c" ;; i32.atomic.rmw8.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\3d" ;; i32.atomic.rmw16.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3e" ;; i64.atomic.rmw8.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\3f" ;; i64.atomic.rmw16.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\40" ;; i64.atomic.rmw32.xor_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\41" ;; i32.atomic.rmw.xchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\42" ;; i64.atomic.rmw.xchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\43" ;; i32.atomic.rmw8.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\fe\44" ;; i32.atomic.rmw16.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\45" ;; i64.atomic.rmw8.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\46" ;; i64.atomic.rmw16.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\fe\47" ;; i64.atomic.rmw32.xchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\48" ;; i32.atomic.rmw.cmpxchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\49" ;; i64.atomic.rmw.cmpxchg
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\41\00" ;; (i32.const 51)
    "\41\00" ;; (i32.const 51)
    "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\02" ;; Alignment of 2
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\41\00" ;; (i32.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\00" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\43" ;; Alignment of 3 with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\11" ;; acqrel memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\42\00" ;; (i64.const 0)
    "\42\00" ;; (i64.const 51)
    "\42\00" ;; (i64.const 51)
    "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u
    "\63" ;; Alignment of 3 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows
    "\01" ;; memory index
    "\00" ;; seqcst memory ordering
    "\00" ;; offset
    "\1a" ;; drop

    "\0b" ;; end
)

;; Execution of acqrel atomics

(module
  (memory 1 1 shared)

  (func (export "init") (param $value i64) (i64.store (i32.const 0) (local.get $value)))

  (func (export "i32.atomic.load") (param $addr i32) (result i32) (i32.atomic.load acqrel (local.get $addr)))
  (func (export "i64.atomic.load") (param $addr i32) (result i64) (i64.atomic.load acqrel (local.get $addr)))
  (func (export "i32.atomic.load8_u") (param $addr i32) (result i32) (i32.atomic.load8_u acqrel (local.get $addr)))
  (func (export "i32.atomic.load16_u") (param $addr i32) (result i32) (i32.atomic.load16_u acqrel (local.get $addr)))
  (func (export "i64.atomic.load8_u") (param $addr i32) (result i64) (i64.atomic.load8_u acqrel (local.get $addr)))
  (func (export "i64.atomic.load16_u") (param $addr i32) (result i64) (i64.atomic.load16_u acqrel (local.get $addr)))
  (func (export "i64.atomic.load32_u") (param $addr i32) (result i64) (i64.atomic.load32_u acqrel (local.get $addr)))

  (func (export "i32.atomic.store") (param $addr i32) (param $value i32) (i32.atomic.store acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.store") (param $addr i32) (param $value i64) (i64.atomic.store acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.store8") (param $addr i32) (param $value i32) (i32.atomic.store8 acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.store16") (param $addr i32) (param $value i32) (i32.atomic.store16 acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.store8") (param $addr i32) (param $value i64) (i64.atomic.store8 acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.store16") (param $addr i32) (param $value i64) (i64.atomic.store16 acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.store32") (param $addr i32) (param $value i64) (i64.atomic.store32 acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.add") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.add acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.add") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.add acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.add_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.add_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.add_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.add_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.add_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.add_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.add_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.add_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.add_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.add_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.sub") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.sub acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.sub") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.sub acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.sub_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.sub_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.sub_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.sub_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.sub_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.sub_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.sub_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.sub_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.sub_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.sub_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.and") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.and acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.and") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.and acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.and_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.and_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.and_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.and_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.and_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.and_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.and_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.and_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.and_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.and_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.or") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.or acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.or") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.or acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.or_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.or_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.or_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.or_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.or_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.or_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.or_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.or_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.or_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.or_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.xor") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.xor acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.xor") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.xor acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.xor_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.xor_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.xor_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.xor_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.xor_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.xor_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.xor_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.xor_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.xor_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.xor_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.xchg") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw.xchg acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw.xchg") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw.xchg acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw8.xchg_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw8.xchg_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i32.atomic.rmw16.xchg_u") (param $addr i32) (param $value i32) (result i32) (i32.atomic.rmw16.xchg_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw8.xchg_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw8.xchg_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw16.xchg_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw16.xchg_u acqrel (local.get $addr) (local.get $value)))
  (func (export "i64.atomic.rmw32.xchg_u") (param $addr i32) (param $value i64) (result i64) (i64.atomic.rmw32.xchg_u acqrel (local.get $addr) (local.get $value)))

  (func (export "i32.atomic.rmw.cmpxchg") (param $addr i32) (param $expected i32) (param $value i32) (result i32) (i32.atomic.rmw.cmpxchg acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i64.atomic.rmw.cmpxchg") (param $addr i32) (param $expected i64) (param $value i64) (result i64) (i64.atomic.rmw.cmpxchg acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i32.atomic.rmw8.cmpxchg_u") (param $addr i32) (param $expected i32) (param $value i32) (result i32) (i32.atomic.rmw8.cmpxchg_u acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i32.atomic.rmw16.cmpxchg_u") (param $addr i32) (param $expected i32) (param $value i32) (result i32) (i32.atomic.rmw16.cmpxchg_u acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i64.atomic.rmw8.cmpxchg_u") (param $addr i32) (param $expected i64) (param $value i64) (result i64) (i64.atomic.rmw8.cmpxchg_u acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i64.atomic.rmw16.cmpxchg_u") (param $addr i32) (param $expected i64) (param $value i64) (result i64) (i64.atomic.rmw16.cmpxchg_u acqrel (local.get $addr) (local.get $expected) (local.get $value)))
  (func (export "i64.atomic.rmw32.cmpxchg_u") (param $addr i32) (param $expected i64) (param $value i64) (result i64) (i64.atomic.rmw32.cmpxchg_u acqrel (local.get $addr) (local.get $expected) (local.get $value)))

)

;; *.atomic.load*

(invoke "init" (i64.const 0x0706050403020100))

(assert_return (invoke "i32.atomic.load" (i32.const 0)) (i32.const 0x03020100))
(assert_return (invoke "i32.atomic.load" (i32.const 4)) (i32.const 0x07060504))

(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0706050403020100))

(assert_return (invoke "i32.atomic.load8_u" (i32.const 0)) (i32.const 0x00))
(assert_return (invoke "i32.atomic.load8_u" (i32.const 5)) (i32.const 0x05))

(assert_return (invoke "i32.atomic.load16_u" (i32.const 0)) (i32.const 0x0100))
(assert_return (invoke "i32.atomic.load16_u" (i32.const 6)) (i32.const 0x0706))

(assert_return (invoke "i64.atomic.load8_u" (i32.const 0)) (i64.const 0x00))
(assert_return (invoke "i64.atomic.load8_u" (i32.const 5)) (i64.const 0x05))

(assert_return (invoke "i64.atomic.load16_u" (i32.const 0)) (i64.const 0x0100))
(assert_return (invoke "i64.atomic.load16_u" (i32.const 6)) (i64.const 0x0706))

(assert_return (invoke "i64.atomic.load32_u" (i32.const 0)) (i64.const 0x03020100))
(assert_return (invoke "i64.atomic.load32_u" (i32.const 4)) (i64.const 0x07060504))

;; *.atomic.store*

(invoke "init" (i64.const 0x0000000000000000))

(assert_return (invoke "i32.atomic.store" (i32.const 0) (i32.const 0xffeeddcc)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x00000000ffeeddcc))

(assert_return (invoke "i64.atomic.store" (i32.const 0) (i64.const 0x0123456789abcdef)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0123456789abcdef))

(assert_return (invoke "i32.atomic.store8" (i32.const 1) (i32.const 0x42)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0123456789ab42ef))

(assert_return (invoke "i32.atomic.store16" (i32.const 4) (i32.const 0x8844)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0123884489ab42ef))

(assert_return (invoke "i64.atomic.store8" (i32.const 1) (i64.const 0x99)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0123884489ab99ef))

(assert_return (invoke "i64.atomic.store16" (i32.const 4) (i64.const 0xcafe)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0123cafe89ab99ef))

(assert_return (invoke "i64.atomic.store32" (i32.const 4) (i64.const 0xdeadbeef)))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0xdeadbeef89ab99ef))

;; *.atomic.rmw*.add

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.add" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111123456789))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.add" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1212121213131313))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.add_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111de))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.add_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111dc0f))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.add_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111153))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.add_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111d000))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.add_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111dbccb7f6))

;; *.atomic.rmw*.sub

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.sub" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111fedcba99))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.sub" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x101010100f0f0f0f))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.sub_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111144))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.sub_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111114613))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.sub_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111cf))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.sub_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111115222))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.sub_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111146556a2c))

;; *.atomic.rmw*.and

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.and" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111110101010))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.and" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0101010100000000))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.and_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111101))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.and_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111110010))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.and_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111100))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.and_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111001))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.and_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111100110001))

;; *.atomic.rmw*.or

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.or" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111113355779))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.or" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111113131313))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.or_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111dd))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.or_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111dbff))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.or_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111153))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.or_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111bfff))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.or_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111dbbbb7f5))

;; *.atomic.rmw*.xor

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.xor" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111103254769))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.xor" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1010101013131313))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.xor_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111dc))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.xor_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111dbef))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.xor_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111153))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.xor_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111affe))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.xor_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111dbaab7f4))

;; *.atomic.rmw*.xchg

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.xchg" (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111112345678))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.xchg" (i32.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0101010102020202))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.xchg_u" (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111cd))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.xchg_u" (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111cafe))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.xchg_u" (i32.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111142))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.xchg_u" (i32.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111beef))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.xchg_u" (i32.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111cabba6e5))

;; *.atomic.rmw*.cmpxchg (compare false)

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.cmpxchg" (i32.const 0) (i32.const 0) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.cmpxchg" (i32.const 0) (i64.const 0) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.cmpxchg_u" (i32.const 0) (i32.const 0) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.cmpxchg_u" (i32.const 0) (i32.const 0x11111111) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111cd))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.cmpxchg_u" (i32.const 0) (i32.const 0) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.cmpxchg_u" (i32.const 0) (i32.const 0x11111111) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111cafe))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.cmpxchg_u" (i32.const 0) (i64.const 0) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.cmpxchg_u" (i32.const 0) (i64.const 0x1111111111111111) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111142))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.cmpxchg_u" (i32.const 0) (i64.const 0) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.cmpxchg_u" (i32.const 0) (i64.const 0x1111111111111111) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111beef))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.cmpxchg_u" (i32.const 0) (i64.const 0) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111111))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.cmpxchg_u" (i32.const 0) (i64.const 0x1111111111111111) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111cabba6e5))

;; *.atomic.rmw*.cmpxchg (compare true)

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw.cmpxchg" (i32.const 0) (i32.const 0x11111111) (i32.const 0x12345678)) (i32.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111112345678))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw.cmpxchg" (i32.const 0) (i64.const 0x1111111111111111) (i64.const 0x0101010102020202)) (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x0101010102020202))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw8.cmpxchg_u" (i32.const 0) (i32.const 0x11) (i32.const 0xcdcdcdcd)) (i32.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111111111cd))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i32.atomic.rmw16.cmpxchg_u" (i32.const 0) (i32.const 0x1111) (i32.const 0xcafecafe)) (i32.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111cafe))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw8.cmpxchg_u" (i32.const 0) (i64.const 0x11) (i64.const 0x4242424242424242)) (i64.const 0x11))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x1111111111111142))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw16.cmpxchg_u" (i32.const 0) (i64.const 0x1111) (i64.const 0xbeefbeefbeefbeef)) (i64.const 0x1111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x111111111111beef))

(invoke "init" (i64.const 0x1111111111111111))
(assert_return (invoke "i64.atomic.rmw32.cmpxchg_u" (i32.const 0) (i64.const 0x11111111) (i64.const 0xcabba6e5cabba6e5)) (i64.const 0x11111111))
(assert_return (invoke "i64.atomic.load" (i32.const 0)) (i64.const 0x11111111cabba6e5))


;; unaligned accesses

(assert_trap (invoke "i32.atomic.load" (i32.const 1)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.load" (i32.const 1)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.load16_u" (i32.const 1)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.load16_u" (i32.const 1)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.load32_u" (i32.const 1)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.store" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.store" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.store16" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.store16" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.store32" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.add" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.add" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.add_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.add_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.add_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.sub" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.sub" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.sub_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.sub_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.sub_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.and" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.and" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.and_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.and_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.and_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.or" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.or" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.or_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.or_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.or_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.xor" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.xor" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.xor_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.xor_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.xor_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.xchg" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.xchg" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.xchg_u" (i32.const 1) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.xchg_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.xchg_u" (i32.const 1) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw.cmpxchg" (i32.const 1) (i32.const 0) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw.cmpxchg" (i32.const 1) (i64.const 0)  (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i32.atomic.rmw16.cmpxchg_u" (i32.const 1) (i32.const 0) (i32.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw16.cmpxchg_u" (i32.const 1) (i64.const 0) (i64.const 0)) "unaligned atomic")
(assert_trap (invoke "i64.atomic.rmw32.cmpxchg_u" (i32.const 1) (i64.const 0) (i64.const 0)) "unaligned atomic")

;; unshared memory is OK
(module
  (memory 1 1)
  (func (drop (i32.atomic.load acqrel (i32.const 0))))
  (func (drop (i64.atomic.load acqrel (i32.const 0))))
  (func (drop (i32.atomic.load16_u acqrel (i32.const 0))))
  (func (drop (i64.atomic.load16_u acqrel (i32.const 0))))
  (func (drop (i64.atomic.load32_u acqrel (i32.const 0))))
  (func       (i32.atomic.store acqrel (i32.const 0) (i32.const 0)))
  (func       (i64.atomic.store acqrel (i32.const 0) (i64.const 0)))
  (func       (i32.atomic.store16 acqrel (i32.const 0) (i32.const 0)))
  (func       (i64.atomic.store16 acqrel (i32.const 0) (i64.const 0)))
  (func       (i64.atomic.store32 acqrel (i32.const 0) (i64.const 0)))
  (func (drop (i32.atomic.rmw.add acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.add acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.add_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.add_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.add_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.sub acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.sub acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.sub_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.sub_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.sub_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.and acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.and acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.and_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.and_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.and_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.or acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.or acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.or_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.or_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.or_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.xor acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.xor acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.xor_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.xor_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.xor_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.xchg acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.xchg acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw16.xchg_u acqrel (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.xchg_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.xchg_u acqrel (i32.const 0) (i64.const 0))))
  (func (drop (i32.atomic.rmw.cmpxchg acqrel (i32.const 0) (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw.cmpxchg acqrel (i32.const 0) (i64.const 0)  (i64.const 0))))
  (func (drop (i32.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i32.const 0) (i32.const 0))))
  (func (drop (i64.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i64.const 0) (i64.const 0))))
  (func (drop (i64.atomic.rmw32.cmpxchg_u acqrel (i32.const 0) (i64.const 0) (i64.const 0))))
)

;; Fails with no memory
(assert_invalid (module (func (drop (i32.atomic.load acqrel (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.load acqrel (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.load16_u acqrel (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.load16_u acqrel (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.load32_u acqrel (i32.const 0))))) "unknown memory")
(assert_invalid (module (func       (i32.atomic.store acqrel (i32.const 0) (i32.const 0)))) "unknown memory")
(assert_invalid (module (func       (i64.atomic.store acqrel (i32.const 0) (i64.const 0)))) "unknown memory")
(assert_invalid (module (func       (i32.atomic.store16 acqrel (i32.const 0) (i32.const 0)))) "unknown memory")
(assert_invalid (module (func       (i64.atomic.store16 acqrel (i32.const 0) (i64.const 0)))) "unknown memory")
(assert_invalid (module (func       (i64.atomic.store32 acqrel (i32.const 0) (i64.const 0)))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.add acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.add acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.add_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.add_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.add_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.sub acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.sub acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.sub_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.sub_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.sub_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.and acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.and acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.and_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.and_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.and_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.or acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.or acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.or_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.or_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.or_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.xor acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.xor acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.xor_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.xor_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.xor_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.xchg acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.xchg acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.xchg_u acqrel (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.xchg_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.xchg_u acqrel (i32.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw.cmpxchg acqrel (i32.const 0) (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw.cmpxchg acqrel (i32.const 0) (i64.const 0)  (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i32.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i32.const 0) (i32.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw16.cmpxchg_u acqrel (i32.const 0) (i64.const 0) (i64.const 0))))) "unknown memory")
(assert_invalid (module (func (drop (i64.atomic.rmw32.cmpxchg_u acqrel (i32.const 0) (i64.const 0) (i64.const 0))))) "unknown memory")