Google GitGoogle Git
Sign in
chromium/chromiumos/third_party/kernel-rebase-patches/d8a3d1e5d3dbf81db7c7313681292b0feea2d8c2/./92f618c053e5aec176718173be16d439041ddee8c48ab7033ffee8ee.patch
blob: 92b6bd42726385a68599b23638fd7e204db0fba3 [file]
From 7e2bb3bf950740847804c74812fc4de9d4f47e2e Mon Sep 17 00:00:00 2001
From: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Date: Fri, 11 Feb 2022 23:14:02 +0800
Subject: [PATCH] CHROMIUM: arm64: dts: mt8186: Add GPU device nodes
Add GPU device nodes for mt8186 SoC.
BUG=b:213000788
TEST=emerge-corsola sys-kernel/chromeos-kernel-5_15
Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Signed-off-by: Nick Fan <Nick.Fan@mediatek.com>
Signed-off-by: Fei Shao <fshao@chromium.org>
Change-Id: I5c48958bd639e097267cc75b5399fdf85491dca6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3329437
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 154 +++++++++++++++++++++--
1 file changed, 145 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 09a72a96a41b56075e578ff1ed7130c7f6540c3c..d756d6966f8931f9468a3c1e9ba6f751a9da3948 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1073,6 +1073,11 @@ efuse: efuse@11cb0000 {
reg = <0 0x11cb0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ gpu_volt_bin: volt-bin {
+ reg = <0x59C 0x4>;
+ bits = <0 3>;
+ };
};
mipi_tx0: dsi-phy@11cc0000 {
@@ -1091,21 +1096,29 @@ mfgsys: clock-controller@13000000 {
#clock-cells = <1>;
};
- gpu: gpu@13040000 {
- compatible = "mediatek,mt8186-mali",
- "arm,mali-bifrost";
+ gpu: mali@13040000 {
+ compatible = "mediatek,mt8186-mali", "arm,mali-bifrost";
reg = <0 0x13040000 0 0x4000>;
-
- clocks = <&mfgsys CLK_MFG_BG3D>;
- interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "job", "mmu", "gpu";
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "gpu", "mmu", "job";
+ clocks = <&topckgen CLK_TOP_MFG>,
+ <&apmixedsys CLK_APMIXED_MFGPLL>,
+ <&apmixedsys CLK_APMIXED_MFGPLL>,
+ <&topckgen CLK_TOP_MAINPLL_D5>,
+ <&mfgsys CLK_MFG_BG3D>;
+ clock-names = "clk_mux",
+ "clk_pll_src",
+ "clk_main_parent",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
<&spm MT8186_POWER_DOMAIN_MFG3>;
power-domain-names = "core0", "core1";
+ nvmem-cells = <&gpu_volt_bin>;
+ nvmem-cell-names = "volt-bin";
#cooling-cells = <2>;
- status = "disabled";
};
mmsys: syscon@14000000 {
@@ -1500,5 +1513,128 @@ larb19: smi@1c10f000 {
mediatek,smi = <&smi_common>;
power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
};
+
+ gpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2", "operating-points-v2-mali";
+ opp-shared;
+
+ opp-299000000 {
+ opp-hz = /bits/ 64 <299000000>;
+ opp-hz-real = /bits/ 64 <299000000>,
+ /bits/ 64 <299000000>;
+ opp-microvolt = <612500>, <850000>;
+ };
+
+ opp-332000000 {
+ opp-hz = /bits/ 64 <332000000>;
+ opp-hz-real = /bits/ 64 <332000000>,
+ /bits/ 64 <332000000>;
+ opp-microvolt = <625000>, <850000>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ opp-hz-real = /bits/ 64 <366000000>,
+ /bits/ 64 <366000000>;
+ opp-microvolt = <637500>, <850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-hz-real = /bits/ 64 <400000000>,
+ /bits/ 64 <400000000>;
+ opp-microvolt = <643750>, <850000>;
+ };
+
+ opp-434000000 {
+ opp-hz = /bits/ 64 <434000000>;
+ opp-hz-real = /bits/ 64 <434000000>,
+ /bits/ 64 <434000000>;
+ opp-microvolt = <656250>, <850000>;
+ };
+
+ opp-484000000 {
+ opp-hz = /bits/ 64 <484000000>;
+ opp-hz-real = /bits/ 64 <484000000>,
+ /bits/ 64 <484000000>;
+ opp-microvolt = <668750>, <850000>;
+ };
+
+ opp-535000000 {
+ opp-hz = /bits/ 64 <535000000>;
+ opp-hz-real = /bits/ 64 <535000000>,
+ /bits/ 64 <535000000>;
+ opp-microvolt = <687500>, <850000>;
+ };
+
+ opp-586000000 {
+ opp-hz = /bits/ 64 <586000000>;
+ opp-hz-real = /bits/ 64 <586000000>,
+ /bits/ 64 <586000000>;
+ opp-microvolt = <700000>, <850000>;
+ };
+
+ opp-637000000 {
+ opp-hz = /bits/ 64 <637000000>;
+ opp-hz-real = /bits/ 64 <637000000>,
+ /bits/ 64 <637000000>;
+ opp-microvolt = <712500>, <850000>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-hz-real = /bits/ 64 <690000000>,
+ /bits/ 64 <690000000>;
+ opp-microvolt = <737500>, <850000>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-hz-real = /bits/ 64 <743000000>,
+ /bits/ 64 <743000000>;
+ opp-microvolt = <756250>, <856250>;
+ };
+
+ opp-796000000 {
+ opp-hz = /bits/ 64 <796000000>;
+ opp-hz-real = /bits/ 64 <796000000>,
+ /bits/ 64 <796000000>;
+ opp-microvolt = <781250>, <881250>;
+ };
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-hz-real = /bits/ 64 <850000000>,
+ /bits/ 64 <850000000>;
+ opp-microvolt = <800000>, <900000>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-hz-real = /bits/ 64 <900000000>,
+ /bits/ 64 <900000000>;
+ opp-microvolt = <850000>, <950000>;
+ opp-microvolt-bin4 = <837500>, <937500>;
+ opp-microvolt-bin5 = <825000>, <925000>;
+ };
+
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-hz-real = /bits/ 64 <950000000>,
+ /bits/ 64 <950000000>;
+ opp-microvolt = <900000>, <1000000>;
+ opp-microvolt-bin4 = <875000>, <975000>;
+ opp-microvolt-bin5 = <850000>, <950000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-hz-real = /bits/ 64 <1000000000>,
+ /bits/ 64 <1000000000>;
+ opp-microvolt = <950000>, <1050000>;
+ opp-microvolt-bin4 = <912500>, <1012500>;
+ opp-microvolt-bin5 = <875000>, <975000>;
+ };
+ };
};
};
--
2.38.3