)]}' { "log": [ { "commit": "13f5f9cd1a0010b352323a9a14b9db55ad07b5e9", "tree": "9e8a98858e281f48b4218c052ddc43ea980a4065", "parents": [ "8f3415382118e5899701df9fb21ff88e76d1c217" ], "author": { "name": "Richard Patel", "email": "me@terorie.dev", "time": "Mon Mar 30 10:31:08 2026" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 30 10:31:08 2026" }, "message": "Add FRED detection (#172)\n\nFRED (Flexible Return and Event Delivery) is a technology enabling\nfaster syscall returns and interrupt handling." }, { "commit": "8f3415382118e5899701df9fb21ff88e76d1c217", "tree": "b7280b1bbc13a232e56f278ff9f988536ad3b988", "parents": [ "f871662950fd6434e19bb056fb1f6efb6eba6144" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Nov 10 11:19:18 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 10 11:19:18 2025" }, "message": "Add AVX512BMM (#170)\n\nBased on https://sourceware.org/pipermail/binutils/2025-November/145449.html" }, { "commit": "f871662950fd6434e19bb056fb1f6efb6eba6144", "tree": "eb4c5b2ee06112c24ff743bbb65dac71ef482b93", "parents": [ "45153321cc88bfab258ba81dad1b69e439a3d67b" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jul 11 09:57:38 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 11 09:57:38 2025" }, "message": "Detect AMD TSA mitigations (#166)\n\nReferences:\n\n* https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7029.html\n* https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf\n\nWill show on all AMD CPUs that are not in the vulnerable range, or use CPUID value." }, { "commit": "45153321cc88bfab258ba81dad1b69e439a3d67b", "tree": "136cc4ba957baa5a528d548b9ec6f935811bc995", "parents": [ "995eb73c79d504ebee25ceb46f564539cfa719c3" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jul 11 09:25:42 2025" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jul 11 09:25:42 2025" }, "message": "Run go mod tidy\n" }, { "commit": "995eb73c79d504ebee25ceb46f564539cfa719c3", "tree": "cad8c456243050934a93362420670f17afd3311e", "parents": [ "fabe6222d225b83c730d59d4779149f3a1a9d8d4" ], "author": { "name": "echiugoog", "email": "edwinchiu+gh@google.com", "time": "Fri Jul 11 09:23:39 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 11 09:23:39 2025" }, "message": "Add in PMU parsing from CPUID leaf 0xA for Intel processors (#165)\n\n* add in PMU parsing\n\n* remove commented out code\n\n* use reflect.DeepEqual instead of testify/assert\n\n* Revert go.mod to fabe622\n\n* remove ARM64 reference as it\u0027s not yet implemented\n\n* simplify parseLeaf0AH\n\n* move parseLeaf0AH to cpuid.go\n\n* move PMU fixed counter support to feature bitfield\n\n* print basic PMU info" }, { "commit": "fabe6222d225b83c730d59d4779149f3a1a9d8d4", "tree": "1b19afa28d31552cee7753506934c05a5cde27ed", "parents": [ "02ba1229f12f8ddd79ea520368e1c4028c21a51d" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Fri Jun 27 05:34:33 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 27 05:34:33 2025" }, "message": "Add SGXPQC detection (#163)\n\ncpuid: Add SGXPQC detection\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "02ba1229f12f8ddd79ea520368e1c4028c21a51d", "tree": "4522c0080a0df000425b4af6989c3afb7d85c1fe", "parents": [ "9258d0f5f488fb3c7294b12074a70ab405f246db" ], "author": { "name": "skartikey", "email": "1942366+skartikey@users.noreply.github.com", "time": "Wed Jun 25 09:40:59 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 25 09:40:59 2025" }, "message": "fix: Fix division by zero in physicalCores on intel (#162)\n\n" }, { "commit": "9258d0f5f488fb3c7294b12074a70ab405f246db", "tree": "7094f0880a2dc7801542711c58751ea32c991b29", "parents": [ "462c017bbfc200ee42e8fb92410c244b8d3bf71e" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Jun 11 12:46:28 2025" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Jun 11 12:46:28 2025" }, "message": "Update testset.\n" }, { "commit": "462c017bbfc200ee42e8fb92410c244b8d3bf71e", "tree": "c8ac097bace9c3af67868ff580cd33d07f9cd532", "parents": [ "668c84e03482d21e107bf4f43da3baf34ac85d62" ], "author": { "name": "Hippolyte Barraud", "email": "hippolyte.barraud@gmail.com", "time": "Wed May 14 07:35:32 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed May 14 07:35:32 2025" }, "message": "darwin/arm64: fix SIMD detection and improve ARM feature probing (#160)\n\n* darwin/arm64: fix SIMD detection and improve ARM feature probing\n\nDetection of Advanced SIMD (NEON) on M1 Macs was broken due to querying\nthe wrong sysctl identifier. Apple\u0027s documentation lists\n\"hw.optional.AdvSIMD\" as the correct identifier, but in reality, it\u0027s\n\"hw.optional.arm.AdvSIMD\" as confirmed by `sysctl -a`. This patch\ncorrects the identifier and adds support for its alias, \"hw.optional\n.neon,\" ensuring proper detection across all models.\n\nAdditionally, this patch revisits all ARM features detected by the\npackage, cross-referencing identifiers (and aliases) against both\nApple\u0027s official sysctl documentation:\n https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics\nand the ARM architecture reference manual:\n https://developer.arm.com/documentation/ddi0487/latest\n\nEach ARM feature now maps to all known sysctl aliases, preventing false\nnegatives and improving detection accuracy on Apple Silicon.\n\n* nit\n\n* fix typo" }, { "commit": "668c84e03482d21e107bf4f43da3baf34ac85d62", "tree": "090c4f938bcf34bacf15f9f8e38e2e779c99a394", "parents": [ "243c6f1c77da5b195532e9ef684c5fd825a099fb" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Wed Mar 19 21:57:52 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Mar 19 21:57:52 2025" }, "message": "Add SM3, SM4 detection on x86 (#157)\n\ncpuid: Add SM3, SM4 detection on x86\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "243c6f1c77da5b195532e9ef684c5fd825a099fb", "tree": "1f15840e2a44eb3c8d6a4edabb67b656107c5ae5", "parents": [ "22ab8b9e7d0bace6b004331e4541a0779db894df" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Mon Mar 10 20:22:22 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Mar 10 20:22:22 2025" }, "message": "Add AMXTRANSPOSE detection (#156)\n\ncpuid: Add AMXTRANSPOSE detection\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "22ab8b9e7d0bace6b004331e4541a0779db894df", "tree": "3e3550684d0c0eb061bc3403c05f2e2c2f73a3fa", "parents": [ "88f6499375272a86d7d7ac59c274412d68a4fb89" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Feb 24 19:37:05 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 24 19:37:05 2025" }, "message": "Update versions \u0026 releaser (#155)\n\n* Update versions \u0026 releaser" }, { "commit": "88f6499375272a86d7d7ac59c274412d68a4fb89", "tree": "673dfcb49f68f66f279d575c88f3e945d35a0056", "parents": [ "68cbe934369c063daf20667abdcd37345bfb6827" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Mon Feb 24 18:22:52 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 24 18:22:52 2025" }, "message": "Add AMXTF32 detection (#154)\n\ncpuid: Add AMXTF32 detection\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "68cbe934369c063daf20667abdcd37345bfb6827", "tree": "524ff4aaae560f9ace7b722662b4120c7fd22f7f", "parents": [ "78c3c03144afe88fbedab38757e27cb1537a3418" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Wed Feb 12 08:52:24 2025" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 12 08:52:24 2025" }, "message": "Add AMXCOMPLEX detection (#153)\n\ncpuid: Add AMXCOMPLEX detection\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "78c3c03144afe88fbedab38757e27cb1537a3418", "tree": "d58710ffcca9f6f130d37546fe5d8d5768d8c150", "parents": [ "ee7cba987ff4d8747807f9e616ac1b8fac8119b9" ], "author": { "name": "Cezar Craciunoiu", "email": "craciunoiu.cezar@yahoo.com", "time": "Thu Nov 28 15:35:06 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Nov 28 15:35:06 2024" }, "message": "Add rest of fields from ID_AA64ISAR0_EL1 (#152)\n\nFeatures added are not yet exposed on darwin, but will probably follow\r\nthe standard from ARM.\r\n\r\nOn the Linux side, hwcap bits are taken from the kernel.\r\n\r\nSigned-off-by: Cezar Craciunoiu \u003ccezar.craciunoiu@gmail.com\u003e" }, { "commit": "ee7cba987ff4d8747807f9e616ac1b8fac8119b9", "tree": "7e004acf98e7e8a1bd51f86f2bf7dbb0f56b1472", "parents": [ "60035f3080f8a64825fc56d16a06103d44e36d4f" ], "author": { "name": "Maksim", "email": "maksim.lopatin.spb@gmail.com", "time": "Sat Oct 26 20:01:32 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Oct 26 20:01:32 2024" }, "message": "Fix threadsPerCore check for Zen 2 (AMD) (#149)\n\nCo-authored-by: Maksim Lopatin \u003clopatinma@mts.ru\u003e" }, { "commit": "60035f3080f8a64825fc56d16a06103d44e36d4f", "tree": "3f45813f8cdfa00beffd362e44ec8cdd8ea3bb19", "parents": [ "92d5326f011e47516a5802a0a98ceaf59b0f98fc" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Tue Oct 22 15:22:02 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 22 15:22:02 2024" }, "message": "cpuid: Add AMX FP8 detection (#148)\n\ncpuid: Add AMXFP8 detection\r\n\r\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "92d5326f011e47516a5802a0a98ceaf59b0f98fc", "tree": "cad2ee9739dbdd0813194885cbab92b50ecfe833", "parents": [ "d25825d28e334335f128a01866428f65b98b86d8" ], "author": { "name": "Brian McGee", "email": "brian@bmcgee.ie", "time": "Mon Aug 05 14:55:49 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Aug 05 14:55:49 2024" }, "message": "Add Hypervisor Vendor (#147)\n\n* fix: vendor id mapping for KVM\r\n\r\nLast few bytes are ascii null characters: \"KVMKVMKVM\\0\\0\\0\". When parsed by `valAsString` this shows up as just \"KVMKVMKVM\".\r\n\r\nTested manually in a QEMU VM with KVM using https://github.com/numtide/nixos-facter.\r\n\r\n* feat: hypervisor vendor\r\n\r\nRead hypervisor vendor as per https://lwn.net/Articles/301888/." }, { "commit": "d25825d28e334335f128a01866428f65b98b86d8", "tree": "051ba0a9c4b0aa1823b81f2924b90f72d6ee1f8f", "parents": [ "95e7626938069ea64e5c91ca2fe36945786fead9" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jul 16 17:30:21 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 16 17:30:21 2024" }, "message": "Add Arm SVE Vector and Predicate lengths (#146)\n\nBumps deps and CI as well." }, { "commit": "95e7626938069ea64e5c91ca2fe36945786fead9", "tree": "15ac6a988702b61b12da633ae7fc7fc986c014be", "parents": [ "486f6ae65fec6bbb15e6f6bff15036f7bc50d4c4" ], "author": { "name": "Oleg Zhurakivskyy", "email": "oleg.zhurakivskyy@intel.com", "time": "Mon Jun 10 09:47:56 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 10 09:47:56 2024" }, "message": "Add AVXVNNIINT16 detection (#144)\n\nSigned-off-by: Oleg Zhurakivskyy \u003coleg.zhurakivskyy@intel.com\u003e" }, { "commit": "486f6ae65fec6bbb15e6f6bff15036f7bc50d4c4", "tree": "302bdeebda388772739cc4a31a97733ada33ec7d", "parents": [ "f89c8c58bdd5348f54ac22d0d58cf797c35bdc2b" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Feb 21 10:21:20 2024" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Feb 21 10:21:20 2024" }, "message": "Add AMD Speculative Return Stack Overflow (SRSO) (#143)\n\nReference: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf" }, { "commit": "f89c8c58bdd5348f54ac22d0d58cf797c35bdc2b", "tree": "3d859e02f414c48c9dd7d4fbf5c23daf3f67392a", "parents": [ "af2b49af3e8339dd30caf1f61039376b920dbcdd" ], "author": { "name": "Lencerf", "email": "changyuan.lv@Gmail.com", "time": "Mon Nov 13 08:26:43 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 13 08:26:43 2023" }, "message": "Add AMD Memory Encrypt detection (#140)\n\nThis patch detects additional information of the AMD Memory Encryption\r\nfeature.\r\n\r\n[0]:\r\nhttps://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf\r\ntable E.4.17\r\n\r\nSigned-off-by: Changyuan Lyu \u003cchangyuanl@google.com\u003e" }, { "commit": "af2b49af3e8339dd30caf1f61039376b920dbcdd", "tree": "c47e4e6315694f7d55d849ceae6ae87d37586d3d", "parents": [ "3a00e73348c959330a0c0346a77696e81fd8dc0d" ], "author": { "name": "Fabiano Fidêncio", "email": "fabiano.fidencio@intel.com", "time": "Mon Nov 06 16:15:15 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 06 16:15:15 2023" }, "message": "workflows: Update actions and golang versions used (#139)\n\n* workflows: Bump golang versions\r\n\r\nSigned-off-by: Fabiano Fidêncio \u003cfabiano.fidencio@intel.com\u003e\r\n\r\n" }, { "commit": "3a00e73348c959330a0c0346a77696e81fd8dc0d", "tree": "55c0d5445a560c8474d8c8a8434453adff500210", "parents": [ "21e1a5b255d75c307a62dd13c98c7deb92c8b629" ], "author": { "name": "Fabiano Fidêncio", "email": "fabiano.fidencio@intel.com", "time": "Mon Nov 06 15:14:15 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Nov 06 15:14:15 2023" }, "message": "Detect TDX Guest when it\u0027s virtualised using Hyper-V (#138)\n\nMicrosoft has decided to purposefully hide the information of the guest\r\nTEE when VMs are being created using Hyper-V.\r\n\r\nThis leads us to check for the Hyper-V cpuid features (0x4000000C), and\r\nthen for the `ebx` value set.\r\n\r\nFor Intel TDX, `ebx` is set as `0xbe3`, being 3 the part we\u0027re mostly\r\ninterested about,according to:\r\nhttps://github.com/torvalds/linux/blob/d2f51b3516dade79269ff45eae2a7668ae711b25/arch/x86/include/asm/hyperv-tlfs.h#L169-L174\r\n\r\nNOTE: On the tests side, we had to manually override the cpuid in order\r\nto avoid the tests failing, and this was suggested by Klaus himself.\r\n\r\nSigned-off-by: Fabiano Fidêncio \u003cfabiano.fidencio@intel.com\u003e" }, { "commit": "21e1a5b255d75c307a62dd13c98c7deb92c8b629", "tree": "60d6cb150ce931663fc5ae001cd16ffe85906ea4", "parents": [ "666b9f56369ee32d4a16c56b0cf8af9074f5fb10" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Oct 31 07:55:08 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Oct 31 07:55:08 2023" }, "message": "Update README.md (#136)\n\n" }, { "commit": "666b9f56369ee32d4a16c56b0cf8af9074f5fb10", "tree": "bac815d6ed3e4171aa186e4f785ea640f7bb9285", "parents": [ "1af2d99c24e60b21f4c8e8ea63ed69523ebbbb16" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jul 25 14:16:48 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 25 14:16:48 2023" }, "message": "Add Intel apx, avx10, keylocker (#134)\n\n* Add Intel APX/AVX10/Keylocker\r\n* Bump CI\r\n* Add to command as well.\r\n\r\nOnly KEYLOCKER has been released in the wild, AFAIK.\r\n" }, { "commit": "1af2d99c24e60b21f4c8e8ea63ed69523ebbbb16", "tree": "20b94e6d9d8b8aa95e5c918898fbffe90da8c391", "parents": [ "7b0c0a2fc0b1f166db5f8d5a78004baea71e8d2c" ], "author": { "name": "Fabiano Fidêncio", "email": "fabiano@fidencio.org", "time": "Fri Jun 02 15:11:24 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 02 15:11:24 2023" }, "message": "Add TDX Guest detection (#132)\n\nWe need to be able to detect that a guest is running using Intel TDX\r\n(Trusted Domain Extensions).\r\n\r\nAs the TDX Guests have their own cpuid leaf (0x21, 0), we can easily\r\ndetected them by checking its cpuid.\r\n\r\nTHe information provided here can be confirmed in the Intel TDX Module\r\nv1.5 Base Architecture Specificication[0], section 11.2 \"Guest TD Run\r\nTime Environment Enumeration\".\r\n\r\nWhat we\u0027re exposing, in the end, is a new feature called \"TDX_GUEST\",\r\nand this is the result of running cpuid with this patch applied on a TDX\r\nguest VM, and on a \"vanilla\" guest VM.\r\n\r\nTDX Guest VM:\r\n```\r\nName:\r\nVendor String: GenuineIntel\r\nVendor ID: Intel\r\nPhysicalCores: 0\r\nThreads Per Core: 1\r\nLogical Cores: 0\r\nCPU Family 6 Model: 143 Stepping: 4\r\nFeatures: ADX,AESNI,AMXBF16,AMXINT8,AMXTILE,AVX,AVX2,AVX512BF16,AVX512BITALG,AVXX\r\n512BW,AVX512CD,AVX512DQ,AVX512F,AVX512FP16,AVX512IFMA,AVX512VBMI,AVX512VBMI2,AVXX\r\n512VL,AVX512VNNI,AVX512VPOPCNTDQ,AVXVNNI,AVXVNNIINT8,BMI1,BMI2,CLDEMOTE,CLMUL,CMM\r\nOV,CMPSB_SCADBS_SHORT,CMPXCHG8,CX16,ERMS,F16C,FLUSH_L1D,FMA3,FSRM,FXSR,FXSROPT,GG\r\nFNI,HLE,HYPERVISOR,IA32_ARCH_CAP,IA32_CORE_CAP,IBPB,LAHF,LZCNT,MD_CLEAR,MMX,MOVBB\r\nE,MOVDIR64B,MOVDIRI,MOVSB_ZL,NX,OSXSAVE,POPCNT,PREFETCHI,RDRAND,RDSEED,RDTSCP,RTT\r\nM,SERIALIZE,SHA,SPEC_CTRL_SSBD,SSE,SSE2,SSE3,SSE4,SSE42,SSSE3,STIBP,STOSB_SHORT,,\r\nSYSCALL,SYSEE,TDX_GUEST,TSXLDTRK,VAES,VPCLMULQDQ,WAITPKG,WBNOINVD,X87,XGETBV1,XSS\r\nAVE,XSAVEC,XSAVEOPT,XSAVES\r\nMicroarchitecture level: 4\r\nCacheline bytes: 64\r\nL1 Instruction Cache: 32768 bytes\r\nL1 Data Cache: 32768 bytes\r\nL2 Cache: 4194304 bytes\r\nL3 Cache: 16777216 bytes\r\nFrequency: 1000000000 Hz\r\n```\r\n\r\nVanilla Guest VM:\r\n```\r\nName: Genuine Intel(R) CPU 0000%@\r\nVendor String: GenuineIntel\r\nVendor ID: Intel\r\nPhysicalCores: 1\r\nThreads Per Core: 1\r\nLogical Cores: 1\r\nCPU Family 6 Model: 143 Stepping: 4\r\nFeatures: ADX,AESNI,AMXBF16,AMXINT8,AMXTILE,AVX,AVX2,AVX512BF16,AVX512BITALG,AVXX\r\n512BW,AVX512CD,AVX512DQ,AVX512F,AVX512FP16,AVX512IFMA,AVX512VBMI,AVX512VBMI2,AVXX\r\n512VL,AVX512VNNI,AVX512VPOPCNTDQ,AVXVNNI,AVXVNNIINT8,BMI1,BMI2,CLDEMOTE,CLMUL,CMM\r\nOV,CMPXCHG8,CX16,ERMS,F16C,FMA3,FSRM,FXSR,FXSROPT,GFNI,HLE,HYPERVISOR,IA32_ARCH__\r\nCAP,IBPB,IBRS,LAHF,LZCNT,MD_CLEAR,MMX,MOVBE,MOVDIR64B,MOVDIRI,NX,OSXSAVE,POPCNT,,\r\nPREFETCHI,RDRAND,RDSEED,RDTSCP,RTM,SERIALIZE,SGX,SGXLC,SHA,SPEC_CTRL_SSBD,SSE,SSS\r\nE2,SSE3,SSE4,SSE42,SSSE3,STIBP,SYSCALL,SYSEE,TSXLDTRK,VAES,VMX,VPCLMULQDQ,WAITPKK\r\nG,WBNOINVD,X87,XGETBV1,XSAVE,XSAVEC,XSAVEOPT,XSAVES\r\nMicroarchitecture level: 4\r\nCacheline bytes: 64\r\nL1 Instruction Cache: 32768 bytes\r\nL1 Data Cache: 32768 bytes\r\nL2 Cache: 4194304 bytes\r\nL3 Cache: 16777216 bytes\r\nSGX: {Available:true LaunchControl:true SGX1Supported:true SGX2Supported:true Maa\r\nxEnclaveSizeNot64:2147483648 MaxEnclaveSize64:72057594037927936 EPCSections:[]}\r\n```\r\n\r\n[0]: https://cdrdv2.intel.com/v1/dl/getContent/733575\r\n\r\nSigned-off-by: Fabiano Fidêncio \u003cfabiano.fidencio@intel.com\u003e" }, { "commit": "7b0c0a2fc0b1f166db5f8d5a78004baea71e8d2c", "tree": "242a7389667203bb87602f06b1aa64ca7953d4e9", "parents": [ "d685acd433f5dde4e315aa5b1eb8e72b9ecce117" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jun 02 14:07:38 2023" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jun 02 14:07:38 2023" }, "message": "Fix AVXVNNIINT8, AVXNECONVERT, PREFETCHI\n\nReplaces #131\n" }, { "commit": "d685acd433f5dde4e315aa5b1eb8e72b9ecce117", "tree": "06b7cdd335a264c30e6e91ef1342e5aaf275851c", "parents": [ "9c5939814b983391297402bb01e64615e62e159b" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sat Feb 25 09:31:40 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Feb 25 09:31:40 2023" }, "message": "Update golang.org/x/sys (#130)\n\n" }, { "commit": "9c5939814b983391297402bb01e64615e62e159b", "tree": "a7143691b5dda3d6e1efd842bdd29f4430b3af2c", "parents": [ "9e22c3618eee5aea2bcc518159aca7e1db75d0c0" ], "author": { "name": "Feruzjon Muyassarov", "email": "feruzjon.muyassarov@intel.com", "time": "Mon Feb 20 14:56:06 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 20 14:56:06 2023" }, "message": "Add more Intel Sierra Forest instructions (#129)\n\nAdd MSRLIST and WRMSRNS Intel Sierra Forest instructions.\r\n\r\nSigned-off-by: Muyassarov, Feruzjon \u003cferuzjon.muyassarov@intel.com\u003e" }, { "commit": "9e22c3618eee5aea2bcc518159aca7e1db75d0c0", "tree": "d4f69d4959ece3cd7ef4ce5acaefcceef51609b3", "parents": [ "dbe27229011c5ebe14c28f96fe52a0f19834e95c" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Feb 03 12:22:14 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Feb 03 12:22:14 2023" }, "message": "Add more Intel mitigation flags (#128)\n\n" }, { "commit": "dbe27229011c5ebe14c28f96fe52a0f19834e95c", "tree": "81c594a8d01c61935c667ddc49271993d51faaa2", "parents": [ "3c0ec06adeb260a595bfb1dff123742e8bac34fb" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Jan 27 16:16:12 2023" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jan 27 16:16:12 2023" }, "message": "Update README.md" }, { "commit": "3c0ec06adeb260a595bfb1dff123742e8bac34fb", "tree": "04a99a27226d458990b01aa2161cb59ce3ee2d47", "parents": [ "8935696eef0584f0ba5bcf62c8f2757f68d084e8" ], "author": { "name": "Feruzjon Muyassarov", "email": "feruzjon.muyassarov@intel.com", "time": "Thu Dec 29 09:58:39 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Dec 29 09:58:39 2022" }, "message": "Add Intel Sierra Forest instructions (#127)\n\nSigned-off-by: Feruzjon Muyassarov \u003cferuzjon.muyassarov@intel.com\u003e\r\n\r\nSigned-off-by: Feruzjon Muyassarov \u003cferuzjon.muyassarov@intel.com\u003e" }, { "commit": "8935696eef0584f0ba5bcf62c8f2757f68d084e8", "tree": "66feba4ca1d62815b66e7995ef0f9153271a2beb", "parents": [ "58b16cf311702cfa8574166750a6a4e4cfa8a288" ], "author": { "name": "Rui Chen", "email": "rui@chenrui.dev", "time": "Thu Dec 15 09:38:54 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Dec 15 09:38:54 2022" }, "message": "docs: add homebrew installation note (#126)\n\n" }, { "commit": "58b16cf311702cfa8574166750a6a4e4cfa8a288", "tree": "0faa92152c414b57a1c5c8ccd975b24eb9de699e", "parents": [ "7181d30b13f682dbb96b1e7d420c3f91e24fbf3d" ], "author": { "name": "Feruzjon Muyassarov", "email": "feruzjon.muyassarov@intel.com", "time": "Wed Dec 07 08:37:51 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Dec 07 08:37:51 2022" }, "message": "Add Intel Granite Rapid features (#125)\n\nDetect Granite Rapid features\r\n\r\n- AMXFP16 - tile computational operations on FP16 numbers\r\n- PREFETCHI - PREFETCHIT0/1 instructions\r\nSigned-off-by: Feruzjon Muyassarov \u003cferuzjon.muyassarov@intel.com\u003e" }, { "commit": "7181d30b13f682dbb96b1e7d420c3f91e24fbf3d", "tree": "45e807190abf2d88825564d25c2ccdc6ffd5d894", "parents": [ "44fdab52ecf9e23168e9b40ac634fbb284005545" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Nov 15 17:17:00 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 15 17:17:00 2022" }, "message": "Fix microarch level (#124)\n\nSYSEE or SYSCALL must be present for microarch level.\r\n\r\nFixes old Intel CPUs having level 0." }, { "commit": "44fdab52ecf9e23168e9b40ac634fbb284005545", "tree": "db78343eb166698eff33ef5a456c75ed4c369032", "parents": [ "1061e99368a4bf76e877a9411a4716034ff47ddc" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Nov 11 11:42:52 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 11 11:42:52 2022" }, "message": "Add more AMD flags (#123)\n\nFrom https://www.amd.com/system/files/TechDocs/55901_0.25.zip" }, { "commit": "1061e99368a4bf76e877a9411a4716034ff47ddc", "tree": "98405fcdff567624ad555315852553e4b9782039", "parents": [ "e32428e6729530015b46da6a4eafce536b19de49" ], "author": { "name": "Christopher Harrington", "email": "ironiridis@gmail.com", "time": "Tue Nov 08 17:11:49 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Nov 08 17:11:49 2022" }, "message": "Darwin L1 Data Cache fix (#122)\n\n* Implement test for Darwin icache/dcache\r\n\r\nCheck that the struct members for the L1 cache match the values provided by the OS sysctl utility\r\n\r\n* Use dcache instead of icache for L1D" }, { "commit": "e32428e6729530015b46da6a4eafce536b19de49", "tree": "9a70f7f615d69c6b8de15e39e00e789b4f6a0a16", "parents": [ "15e250da8e23097acfd9c50b3855179c76a2ab0a" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Nov 04 15:10:57 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 04 15:10:57 2022" }, "message": "Update README.md" }, { "commit": "15e250da8e23097acfd9c50b3855179c76a2ab0a", "tree": "e15c362d9e708d18a7d88d2116b22b90df9b15e7", "parents": [ "9cda38163a537ceec13e09ec11ee6475b5d16728" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Oct 14 09:04:58 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Oct 14 09:04:58 2022" }, "message": "Add CombineFeatures for faster lookups. (#120)\n\nSmall change, change `Has` to pointer receiver." }, { "commit": "9cda38163a537ceec13e09ec11ee6475b5d16728", "tree": "5ccb05aa50f1dce41c2d1515f4bbebce5bc00a5d", "parents": [ "f02e77d58575dc0dd7ec7cf62dca9eff96d466cb" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Oct 10 13:35:32 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Oct 10 13:35:32 2022" }, "message": "Add some Intel flags (#119)\n\n" }, { "commit": "f02e77d58575dc0dd7ec7cf62dca9eff96d466cb", "tree": "198108d32452423c5a650bb552a725f4cda9a6fc", "parents": [ "976c6486fb9f5d9ef7354ef9c2819b1ffcda73a9" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Sep 27 11:11:40 2022" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Sep 27 11:11:40 2022" }, "message": "Update testset.\n" }, { "commit": "976c6486fb9f5d9ef7354ef9c2819b1ffcda73a9", "tree": "afedc589c43959077211f8d5086b7e910f2c967e", "parents": [ "b27ab7bf74513aae0b87715957f99650d2f8a91d" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Aug 26 10:02:30 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Aug 26 10:02:30 2022" }, "message": "Skip AMD leaf 0x8000001d parsing if no TOPEXT (#118)\n\n* Skip AMD leaf 0x8000001d parsing if no TOPEXT\r\n\r\nAdd flag for TopologyExtensions, use it when detecting.\r\n\r\nFixes #117\r\n\r\n* Upgrade CI to Go 1.19" }, { "commit": "b27ab7bf74513aae0b87715957f99650d2f8a91d", "tree": "96290248ee5cf0eab702b7b931937e6ae4d18dbe", "parents": [ "45f166130b70caa073e0434192b876263c97f47d" ], "author": { "name": "Fernando Pelliccioni", "email": "fpelliccioni@gmail.com", "time": "Mon Jul 25 11:47:59 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 25 11:47:59 2022" }, "message": "Fixes MMXEXT (#116)\n\nMMXEXT is defined in https://github.com/klauspost/cpuid/blob/45f166130b70caa073e0434192b876263c97f47d/cpuid.go#L1188\r\nThe removed line corresponds to `ACPI` according to https://en.wikipedia.org/wiki/CPUID#EAX\u003d1:_Processor_Info_and_Feature_Bits" }, { "commit": "45f166130b70caa073e0434192b876263c97f47d", "tree": "b21da707d6a8f4bdb4babab571a369a602d26380", "parents": [ "3e75088cc54eafef984779a72087e3523bf3281f" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jul 25 11:16:46 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 25 11:16:46 2022" }, "message": "Remove SCE (#115)\n\n* Remove SCE\r\n\r\nRemove SCE, since it was likely wrong.\r\n\r\nReplaced by `SYSCALL` and `SYSEE` which are clearer. Use whichever you meant.\r\n\r\nCo-authored-by: Fernando Pelliccioni \u003cfpelliccioni@gmail.com\u003e" }, { "commit": "3e75088cc54eafef984779a72087e3523bf3281f", "tree": "84283a591e9a67a3a644ac4ba69bd5bbdeafbee1", "parents": [ "a91526e3f158d27bf8cdfe50719b61b9f958fb6e" ], "author": { "name": "Fernando Pelliccioni", "email": "fpelliccioni@gmail.com", "time": "Thu Jul 21 10:18:54 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 21 10:18:54 2022" }, "message": "Code consistency (#114)\n\n" }, { "commit": "a91526e3f158d27bf8cdfe50719b61b9f958fb6e", "tree": "83359eaeecd48194c7e417c8c9de4ca16f5bebdb", "parents": [ "4645384556483379792c7a2ac8fcacaf5d80141b" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Thu Jul 14 16:07:31 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 14 16:07:31 2022" }, "message": "Add CPU Stepping (#112)\n\nAnd fix family/model for very old CPUs.\r\n\r\nFixes #111" }, { "commit": "4645384556483379792c7a2ac8fcacaf5d80141b", "tree": "a0d2e2819d08334b16b052b95a5e2f6408012d44", "parents": [ "5a76678e8d7f2d8bae05356fd3c3d64467c93e1f" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jul 11 12:33:11 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 11 12:33:11 2022" }, "message": "Add Intel Leaf 7, branch 1 (#110)\n\n* Add Intel Leaf 7, branch 1\r\n* Update test db." }, { "commit": "5a76678e8d7f2d8bae05356fd3c3d64467c93e1f", "tree": "95cce7d1a95d36c44c1aeead37ad58a2ca193199", "parents": [ "b4a7e656b48dc25ccb72fbea2967de59ebf3896c" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sun Jul 10 17:15:40 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jul 10 17:15:40 2022" }, "message": "Add AMD SVM features (#109)\n\n" }, { "commit": "b4a7e656b48dc25ccb72fbea2967de59ebf3896c", "tree": "bbd59721c94d5f11dd856a316c058d9d595029bd", "parents": [ "2c6b0c94578b1fda85ed6dc5b18c0898fc168584" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sat Jul 09 17:40:33 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Jul 09 17:40:33 2022" }, "message": "Relax detection of features that have non-avx512 versions (#108)\n\nGFNI, VAES and VPCLMULQDQ does not require AVX512, so detect them even if avx512 isn\u0027t available." }, { "commit": "2c6b0c94578b1fda85ed6dc5b18c0898fc168584", "tree": "a3e5c8d2b380507ec5ee9f3fdb422a6106797fa2", "parents": [ "2a5efe88e9da9822cfdde4f6f68cf47b1202e86a" ], "author": { "name": "Baptiste Canton", "email": "bat@sbz.fr", "time": "Sat Jul 09 15:25:45 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sat Jul 09 15:25:45 2022" }, "message": "Try to fill darwin arm64 from sysctl (#105)\n\n* fill CPUInfo on darwin arm64\r\n" }, { "commit": "2a5efe88e9da9822cfdde4f6f68cf47b1202e86a", "tree": "e7ceb9385260a0dc478545cf6e9e06df97c2bc43", "parents": [ "63ef1e510c4df12437d64f59d7abf639e9c28903" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jun 21 09:10:55 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 21 09:10:55 2022" }, "message": "Fix AMD cache hang on buggy Xen hypervisor (#104)\n\nXen Hypervisor is buggy and returns the same entry no matter ECX value.\r\nHack: When we encounter the same entry 100 times we break.\r\n\r\nFixes #103" }, { "commit": "63ef1e510c4df12437d64f59d7abf639e9c28903", "tree": "91eafad7dc5dd6ea69b71b321f961b4a02cd4271", "parents": [ "d0ede562a40d11b8d7fbc566e7b496aa4bab813d" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sun Jun 12 16:18:10 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jun 12 16:18:10 2022" }, "message": "Add Intel TME detection (#102)\n\nFrom Intel® Architecture Instruction Set Extensions and Future Features\r\n\r\nPCONFIG information is not really explained." }, { "commit": "d0ede562a40d11b8d7fbc566e7b496aa4bab813d", "tree": "8cc1f0149013c104bc943331e1a4779cca6e7308", "parents": [ "504b1fda66e7cb2396ac46443380f61c7006cbbe" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sun Jun 12 14:11:39 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jun 12 14:11:39 2022" }, "message": "Add AMD SEV/SME feature detection (#100)\n\nReference: E.4.17 Function 8000_001Fh—Encrypted Memory Capabilities from AMD64 Architecture Programmer’s Manual, Volume 3: General-Purpose and System Instructions." }, { "commit": "504b1fda66e7cb2396ac46443380f61c7006cbbe", "tree": "167ab18d7a954331a18ed467e57af8bb89b817f0", "parents": [ "b63c559cd8aecb246faafb616587aa9ab93fecba" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Sun Jun 12 14:11:26 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Jun 12 14:11:26 2022" }, "message": "ci: Bump Go to v1.18 (#101)\n\n* ci: Bump Go to v1.18\r\n* Bump goreleaser" }, { "commit": "b63c559cd8aecb246faafb616587aa9ab93fecba", "tree": "c4920be8d142353fcbf485131219ef0e0a7112c7", "parents": [ "7062fc0aad4f12f417c112b14ee2a5a42570d9ae" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Thu May 05 15:47:53 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 05 15:47:53 2022" }, "message": "Add leaf 13 parsing. (#97)\n\n" }, { "commit": "7062fc0aad4f12f417c112b14ee2a5a42570d9ae", "tree": "d6c0fd679173cc987e4f51d531ad52c563a11dca", "parents": [ "65b27688b98c471a6e753703ca16c3325d20ef80" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Mar 18 16:07:20 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 18 16:07:20 2022" }, "message": "Update README.md" }, { "commit": "65b27688b98c471a6e753703ca16c3325d20ef80", "tree": "9f7a22490b945a058caeffecd30f3d9822fdf922", "parents": [ "a4e6a85211cb56ee3d53b6832925f88f47b6d2bb" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Mar 18 15:29:57 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 18 15:29:57 2022" }, "message": "Add CPU level test (#96)\n\nExample: `cpuid -check-level\u003d4`" }, { "commit": "a4e6a85211cb56ee3d53b6832925f88f47b6d2bb", "tree": "7e04170a21bc55d9c12e7c862ee9125b07407c57", "parents": [ "1a69123a01890d225d7cc8a908c732f8fcb683d3" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Feb 08 16:13:37 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Feb 08 16:13:37 2022" }, "message": "Add Features to JSON output (#94)\n\n.. and X64Level" }, { "commit": "1a69123a01890d225d7cc8a908c732f8fcb683d3", "tree": "a2096829ecad8d9b20ccb322692e541739cc5074", "parents": [ "eb76847d2697562b682465809ec93a3a9df61404" ], "author": { "name": "Mikko Ylinen", "email": "mikko.ylinen@intel.com", "time": "Mon Feb 07 18:35:02 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 07 18:35:02 2022" }, "message": "Detect Control-flow Enforcement Technology (CET) bits (#93)\n\nSigned-off-by: Mikko Ylinen \u003cmikko.ylinen@intel.com\u003e" }, { "commit": "eb76847d2697562b682465809ec93a3a9df61404", "tree": "e80cb518dc6d050df6571d3ee84e6196adfd0aeb", "parents": [ "cffd0d4c86d45f8de353e162651c92fa263e845d" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jan 31 14:03:13 2022" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jan 31 14:03:13 2022" }, "message": "Add Microarchitecture levels (#92)\n\nFrom https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels\r\n\r\nExample:\r\n```\r\nName: AMD Ryzen 9 3950X 16-Core Processor\r\nVendor String: AuthenticAMD\r\nVendor ID: AMD\r\nPhysicalCores: 16\r\nThreads Per Core: 2\r\nLogical Cores: 32\r\nCPU Family 23 Model: 113\r\nFeatures: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CLZERO,CMOV,CMPXCHG8,CPBOOST,CX16,F16C,FMA3,FXSR,FXSROPT,HTT,HYPERVISOR,LAHF,LZCNT,MCAOVERFLOW,MMX,MMXEXT,MOVBE,NX,OSXSAVE,POPCNT,RDRAND,RDSEED,RDTSCP,SCE,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3,SUCCOR,X87,XSAVE\r\nMicroarchitecture level: 3\r\nCacheline bytes: 64\r\nL1 Instruction Cache: 32768 bytes\r\nL1 Data Cache: 32768 bytes\r\nL2 Cache: 524288 bytes\r\nL3 Cache: 16777216 bytes\r\n```" }, { "commit": "cffd0d4c86d45f8de353e162651c92fa263e845d", "tree": "a28e7acb5447bbbea45eb498822392460539e412", "parents": [ "e6371685422577adc679b48b292447e2bf0fff03" ], "author": { "name": "Ibrahim Fadel", "email": "ibrahim.m.fadel@gmail.com", "time": "Tue Sep 28 09:30:23 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Sep 28 09:30:23 2021" }, "message": "fix readme example code to print instruction cache instead of data cache for the second time, also remove unecessary fmt.Sprintf (#91)\n\n" }, { "commit": "e6371685422577adc679b48b292447e2bf0fff03", "tree": "bae95c7ca802b698a4da356bc58a8ff1c63dfc92", "parents": [ "c23d62f83b530ff203001f7f42b2c4c896b27e54" ], "author": { "name": "Mostyn Bramley-Moore", "email": "mostyn@antipode.se", "time": "Sun Sep 19 10:54:47 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Sun Sep 19 10:54:47 2021" }, "message": "Fix some lint warnings (#90)\n\n* Don\u0027t use fmt.Sprintf if we don\u0027t use any formatting\r\n* append multiple elements instead of calling append multiple times\r\n* Comment out a dead if branch\r\n* Remove superfluous return" }, { "commit": "c23d62f83b530ff203001f7f42b2c4c896b27e54", "tree": "4ae631c9b897c45ff18b23287f4a4a27d04583a0", "parents": [ "fc704489f9beb7ba1054d43d0024fb71a76809e6" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Sep 14 08:18:51 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Sep 14 08:18:51 2021" }, "message": "Bump CI/CD versions (#88)\n\nTest on Go 1.17" }, { "commit": "fc704489f9beb7ba1054d43d0024fb71a76809e6", "tree": "5913b585780b91f27ff501cbf25b318460daf3b5", "parents": [ "6903d4066801a7d800d4537ee9eebe81ea97000e" ], "author": { "name": "Tobias Klauser", "email": "tklauser@distanz.ch", "time": "Tue Sep 14 08:18:31 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Sep 14 08:18:31 2021" }, "message": "Add //go:build lines (#89)\n\nStarting with Go 1.17, `//go:build` lines are preferred over `// +build`\r\nlines, see https://golang.org/doc/go1.17#build-lines and\r\nhttps://golang.org/design/draft-gobuild for details.\r\n\r\nThis change was generated by running Go 1.17 `gofmt` which automatically\r\nadds `//go:build` lines based on the existing `// +build` lines." }, { "commit": "6903d4066801a7d800d4537ee9eebe81ea97000e", "tree": "24e5220a21d45923b4168ad051729e649d19afcf", "parents": [ "8b74771ac394af3334d64594d87be01b9ed91aa0" ], "author": { "name": "Mikko Ylinen", "email": "mikko.ylinen@intel.com", "time": "Fri Jul 30 06:58:55 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 30 06:58:55 2021" }, "message": "Detect AVX512 Half-precision floating point (FP16) (#83)\n\nAVX512 FP16 instructions are supported when\nCPUID.(EAX\u003d7,ECX\u003d0):EDX[bit 23] is present.\n\nSigned-off-by: Mikko Ylinen \u003cmikko.ylinen@intel.com\u003e" }, { "commit": "8b74771ac394af3334d64594d87be01b9ed91aa0", "tree": "6cfaf942a93aa06fd095e403221122ed795dda18", "parents": [ "30cc3e6bc7857707fda06af3db35bc732051b34a" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Jul 07 07:21:37 2021" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Jul 07 07:21:37 2021" }, "message": "Remove debug print.\n" }, { "commit": "30cc3e6bc7857707fda06af3db35bc732051b34a", "tree": "eabc39d31b4e5a2987c9c31777b54ea0b28f776c", "parents": [ "4150c1cea2fd77c9a5e7bc59bb70566ddf7d4cc0" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jun 29 11:06:36 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 29 11:06:36 2021" }, "message": "Do releases with workflows (#80)\n\nDitch travis." }, { "commit": "4150c1cea2fd77c9a5e7bc59bb70566ddf7d4cc0", "tree": "40d9893bcbbedffd0495f418720f0fa0c27a7382", "parents": [ "93795d936a98bae91dfeb8816bc039a89bcb6413" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jun 29 10:33:52 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 29 10:33:52 2021" }, "message": "Add flags and CPU boost freq (#78)\n\nBoost is Intel only so far." }, { "commit": "93795d936a98bae91dfeb8816bc039a89bcb6413", "tree": "659d520860d420d72c6780a7f7b3a9583f611861", "parents": [ "c6a3519c8125843cc14161fb2349bc3fd8b19643" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Jun 29 10:33:30 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 29 10:33:30 2021" }, "message": "Add Go workflow (#79)\n\n" }, { "commit": "c6a3519c8125843cc14161fb2349bc3fd8b19643", "tree": "69154ca7e20aacee89e521d0e48cb7d12c09b72d", "parents": [ "3df0045a253fe31eb023acb0af594154c433fef7" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Mar 26 09:49:37 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Mar 26 09:49:37 2021" }, "message": "Add darwin AVX512 detection (#74)\n\n* Add darwin AVX512 detection\r\n\r\nImported from https://go-review.googlesource.com/c/sys/+/285572/\r\n\r\nSee https://github.com/golang/go/issues/43089\r\n" }, { "commit": "3df0045a253fe31eb023acb0af594154c433fef7", "tree": "686d9fa116bfd96c3c481e3cd7db3e3e5bbff20a", "parents": [ "6c7be61986154081d0efd7b81197bccda486a450" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Mar 17 14:11:03 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Mar 17 14:11:03 2021" }, "message": "Add cpuid executable (#73)\n\n* Add cpuid executable" }, { "commit": "6c7be61986154081d0efd7b81197bccda486a450", "tree": "594d3fd3f15dfaf117ac8db46193a6eab56f13c3", "parents": [ "11274af0a6d540f8fcfec0d5ed78fbe6f42c3ee3" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Mar 17 13:18:06 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Mar 17 13:18:06 2021" }, "message": "Add \"nounsafe\" tag (#72)\n\nAdds `tags\u003dnounsafe` \r\n\r\n" }, { "commit": "11274af0a6d540f8fcfec0d5ed78fbe6f42c3ee3", "tree": "9d027bcb49babcfc4431f17bb606f87883f77e1b", "parents": [ "e090e00dd332fb26d10115e9759f027e1927005b" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Feb 22 17:09:59 2021" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Feb 22 17:09:59 2021" }, "message": "Test all archs (#71)\n\n* Test all archs\r\n" }, { "commit": "e090e00dd332fb26d10115e9759f027e1927005b", "tree": "36c65e9fc3fac6ca297c892f525deafb4afc1c63", "parents": [ "d1038c4e95c2ddf4485f99ab0eb39b454358cd71" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Feb 22 15:27:34 2021" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Feb 22 15:27:34 2021" }, "message": "Fix 386/appengine\n" }, { "commit": "d1038c4e95c2ddf4485f99ab0eb39b454358cd71", "tree": "365c21c5af32381f0e6354a20540e9deec47fd33", "parents": [ "e6213a41e5c191772628cc634d104be2e51d4f2a" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Dec 18 08:11:28 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 18 08:11:28 2020" }, "message": "Add cpu.features flag (#68)\n\n* Add cpu.features flag\r\n\r\nWill display features and exit." }, { "commit": "e6213a41e5c191772628cc634d104be2e51d4f2a", "tree": "70b588cec29c0cc794e2cdc8dd1dfe68d5ec15c1", "parents": [ "38c313ae9e5747846d9cf5bf71ec54801663c4a3" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Dec 18 08:11:13 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 18 08:11:13 2020" }, "message": "Add Has(feature) to check single feature (#69)\n\n* Add Has(feature) to check single feature\r\n\r\nThis function can likely be inlined.\r\n\r\n" }, { "commit": "38c313ae9e5747846d9cf5bf71ec54801663c4a3", "tree": "e534e0d67cd85d535d1e15238742293f65b16594", "parents": [ "e6f7cd973f761fa2cecb6f7b4e567164fa85c6c0" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Dec 09 10:25:09 2020" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Dec 09 10:25:09 2020" }, "message": "fma 3 still requires OSXSAVE\n" }, { "commit": "e6f7cd973f761fa2cecb6f7b4e567164fa85c6c0", "tree": "875ea7cf254cdaf75d17f8301491d4d703c9f349", "parents": [ "05e0b1dfcdc052329c668d84a5696c7d2b390360" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Dec 09 09:12:18 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Dec 09 09:12:18 2020" }, "message": "Detect ARM64 affinity cores (#67)\n\nUse `sched_getaffinity` to get a logical/physical core count.\r\n\r\nThis is of course not completely reliable, but is better than nothing.\r\n\r\nTrust ARMCPUID and try to get some more information, like vendor, etc." }, { "commit": "05e0b1dfcdc052329c668d84a5696c7d2b390360", "tree": "8e2324ac527627ff9b80302f2481059b1620cdab", "parents": [ "46da2cfe27ff995181e56cdd8bcee67d3b8575c5" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Dec 09 09:11:38 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Dec 09 09:11:38 2020" }, "message": "FMA3 without AVX (#65)\n\nMartin Moehrmann:\r\n\r\n\u003e As I learned recently FMA only really requires OSXSAVE as per intel manual.\r\n\u003e so while uncommon someone might use FMA with sse registers on machine with no AVX or support to store and restore YMM registers.\r\n\u003e also know as users still using windows vista kernels" }, { "commit": "46da2cfe27ff995181e56cdd8bcee67d3b8575c5", "tree": "cef1237c518565ff9ba80cdc90e895f5ba5d14d9", "parents": [ "23e01ae8a150f66375d25ea1f1d52031fc3da4b9" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 12:13:09 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 08 12:13:09 2020" }, "message": "Update README.md" }, { "commit": "23e01ae8a150f66375d25ea1f1d52031fc3da4b9", "tree": "03e6aa3a90c0e5e2f0b83989fdbbe4b5f43b790d", "parents": [ "4c872f36d0b12aa3c19b376252b29e12037cb127" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 11:47:31 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 08 11:47:31 2020" }, "message": "Update README.md" }, { "commit": "4c872f36d0b12aa3c19b376252b29e12037cb127", "tree": "eac3f0072b815cc851d32c6d12b5ece6a2e2a3e6", "parents": [ "aa268cd09e03568a2dd336b4272eabdc24ed4157" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 11:45:55 2020" }, "committer": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 11:45:55 2020" }, "message": "Update go.mod to v2\n" }, { "commit": "aa268cd09e03568a2dd336b4272eabdc24ed4157", "tree": "9cb8b625bb5df9a1fb5c3822f4fa4dc68da37ace", "parents": [ "b0c8da32393f23e9fc9e7c38235ce6c1f6dd5983" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 11:38:49 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 08 11:38:49 2020" }, "message": "Update README.md" }, { "commit": "b0c8da32393f23e9fc9e7c38235ce6c1f6dd5983", "tree": "29970e24803aa63a0e514ac898c4fba240b1b31d", "parents": [ "43f4c41326096a3d90b250136a41d7e0c46bbcd8" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 11:05:19 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 08 11:05:19 2020" }, "message": "Fix ARM64 and add fallback (#64)\n\nFix typo, LOL\r\n\r\nAdd \"/proc/self/auxv\" fallback.\r\n" }, { "commit": "43f4c41326096a3d90b250136a41d7e0c46bbcd8", "tree": "a127ae187d6188d8202efdd42f6f8b9151ba4ab3", "parents": [ "eae48960b2237aa165fec2b5d831e25658f5d195" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue Dec 08 09:50:35 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Dec 08 09:50:35 2020" }, "message": "v2 refactor and API changes (#62)\n\nRefactors the API to make it smaller and easier to maintain.\r\n\r\nAdds ARM64 detection.\r\n\r\nMany tweaks and fixes.\r\n\r\nFixes #23\r\nFixes #52\r\nFixes #63\r\nFixes #4 (a bit more)\r\nReplaces #31\r\n" }, { "commit": "eae48960b2237aa165fec2b5d831e25658f5d195", "tree": "9bb8725a31399038c0d2b8b9e63bde1d3d053c3d", "parents": [ "242d0b0aa2074c8ed7e32b965696980048c634de" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Fri Dec 04 11:57:25 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Dec 04 11:57:25 2020" }, "message": "Remove the private package (#61)\n\n" }, { "commit": "242d0b0aa2074c8ed7e32b965696980048c634de", "tree": "a601d48c4df275b061bb428ee7bc339c37865fd1", "parents": [ "321795ade971394838f6f58a88ab27490143f97f" ], "author": { "name": "Antti Kervinen", "email": "antti.kervinen@intel.com", "time": "Fri Nov 27 15:03:41 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 27 15:03:41 2020" }, "message": "Detect Sapphire Rapids features (#60)\n\n- WAITPKG: TPAUSE, UMONITOR, UMWAIT\r\n- SERIALIZE: Serialize Instruction Execution\r\n- TSXLDTRK: Intel TSX Suspend Load Address Tracking\r\n- WBNOINVD: Write Back and Do Not Invalidate Cache\r\n- MOVDIRI: Move Doubleword as Direct Store\r\n- MOVDIR64B: Move 64 Bytes as Direct Store\r\n- ENQCMD: Enqueue Command\r\n- CLDEMOTE: Cache Line Demote\r\n\r\nSigned-off-by: Antti Kervinen \u003cantti.kervinen@intel.com\u003e" }, { "commit": "321795ade971394838f6f58a88ab27490143f97f", "tree": "6b112b78dd7cd06030695c1157ccce3a8d5fcafe", "parents": [ "c8c1820075900becfd4ebb05ea010608bbbfc393" ], "author": { "name": "Mikko Ylinen", "email": "mikko.ylinen@intel.com", "time": "Fri Nov 27 14:35:51 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Nov 27 14:35:51 2020" }, "message": "v2: Move x86 CPU features from Flags to a FlagSet (#59)\n\n* Move x86 CPU features from Flags to a FlagSet\r\n\r\nNotes on backwards compatibility:\r\n\r\n* CPUID consts had to change from 1 \u003c\u003c iota to iota\r\n* CPU.Features is kept as is for old features\r\n\r\nThis change deprecates CPU.Features due to a limitation of only\r\n64 feature bits available when using Flags type (uint64).\r\n\r\nThe new method introduces a FlagSet with an array of Flags.\r\n\r\nSigned-off-by: Mikko Ylinen \u003cmikko.ylinen@intel.com\u003e\r\n" }, { "commit": "c8c1820075900becfd4ebb05ea010608bbbfc393", "tree": "39d0016b76a15f23b5bd8776b6be7c312f3076a1", "parents": [ "fc8eb62d0b3172de22845604984aa48abe034d4e" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Wed Aug 12 11:43:33 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Aug 12 11:43:33 2020" }, "message": "Print CI CPU features (#58)\n\n* Print CI CPU features\r\n* Print ARM+AMX\r\n* Update test to Go 1.15.x" }, { "commit": "fc8eb62d0b3172de22845604984aa48abe034d4e", "tree": "28f1b4b25a2fd8c39828a5379968d0b7e92aafe9", "parents": [ "750c0591dbbd50ef88371c665ad49e426a4b830b" ], "author": { "name": "Antti Kervinen", "email": "antti.kervinen@intel.com", "time": "Thu Jul 16 10:14:13 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 16 10:14:13 2020" }, "message": "Add CPUInfo.AmxFeatures, detect AMXBF16, AMXTILE and AMXINT8 (#56)\n\n- CPUInfo.Features has run out of space. Therefore following features\r\n are added under separate feature flags (CPUInfo.AmxFeatures), as\r\n discussed in Issue #55.\r\n- AMXBF16 - Tile computational operations on BFLOAT16 numbers\r\n- AMXTILE - Tile architecture\r\n- AMXINT8 - Tile computational operations on 8-bit integers\r\n\r\nSigned-off-by: Antti Kervinen \u003cantti.kervinen@intel.com\u003e" }, { "commit": "750c0591dbbd50ef88371c665ad49e426a4b830b", "tree": "87ed57531ab66831c3a4a749b99cda8b1a50a4f3", "parents": [ "b47a6aa133a439b855be0344e113d78108b959bd" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jul 06 09:27:20 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 06 09:27:20 2020" }, "message": "Disable arm64 (#54)\n\n* Disable ARM64 until #52 is resolved." }, { "commit": "b47a6aa133a439b855be0344e113d78108b959bd", "tree": "9ddc022ffcea2e2be482284fa338866c7f078372", "parents": [ "deab41a65a4a2a1791efd0c44b214c74caf8dc5e" ], "author": { "name": "Junpei Kawamoto", "email": "kawamoto.junpei@gmail.com", "time": "Fri Jun 26 10:45:32 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 26 10:45:32 2020" }, "message": "Fix missing noasm tags (#50)\n\n" }, { "commit": "deab41a65a4a2a1791efd0c44b214c74caf8dc5e", "tree": "68ad02b72ce4f9d661d08c53a02f19928038ee5a", "parents": [ "8c1866273bcef8cd2fd365b8c0c11ab304568964" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jun 01 19:06:52 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 01 19:06:52 2020" }, "message": "Update README.md" }, { "commit": "8c1866273bcef8cd2fd365b8c0c11ab304568964", "tree": "8ec4315145236a76b14f4b5d252b613d696a512a", "parents": [ "1b338842ec1bd36f264292d5334fefd33b861b22" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jun 01 19:06:38 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 01 19:06:38 2020" }, "message": "Update README.md" }, { "commit": "1b338842ec1bd36f264292d5334fefd33b861b22", "tree": "ed9a756bad99027b32fcf25c266d2cbeed06ee24", "parents": [ "7a07d3a53fd71ba4362eda3b3b707212848ae77a" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Mon Jun 01 17:19:26 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 01 17:19:26 2020" }, "message": "Clean up ARM (#48)\n\n* Clean up ARM stuff." }, { "commit": "7a07d3a53fd71ba4362eda3b3b707212848ae77a", "tree": "c00a98313634547e41bfce1ba906152eabbdee46", "parents": [ "c17dbe944b7800a1bf7c0f814774541447406b6e" ], "author": { "name": "Frank Wessels", "email": "fwessels@xs4all.nl", "time": "Mon Jun 01 08:31:51 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 01 08:31:51 2020" }, "message": "Enable feature detection for arm64 (#44)\n\n* Enable feature detection for arm64\r\n" }, { "commit": "c17dbe944b7800a1bf7c0f814774541447406b6e", "tree": "2a00ed99e941d738af9c3746ac409300071426c9", "parents": [ "0b33da1ab55444064002aed71f680559fe5fd2b0" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Thu May 28 17:00:47 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 28 17:00:47 2020" }, "message": "Add noasm tag. (#47)\n\n" }, { "commit": "0b33da1ab55444064002aed71f680559fe5fd2b0", "tree": "1e2d29149e9a9d0451e670cbbf27f5d119dfd98e", "parents": [ "e2520679b49a51d0fdb37d6c5704fa2de2949616" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Thu May 28 09:03:07 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu May 28 09:03:07 2020" }, "message": "Update Travis CI (#45)\n\n* Update Travis CI" }, { "commit": "e2520679b49a51d0fdb37d6c5704fa2de2949616", "tree": "69ef901a0a25982374d76c92429688f7787431eb", "parents": [ "7799af8a0632c7898e09de3cfa60ffc938691aad" ], "author": { "name": "Klaus Post", "email": "klauspost@gmail.com", "time": "Tue May 26 13:53:38 2020" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue May 26 13:53:38 2020" }, "message": "Add raw vendor string (#43)\n\nFixes #42" } ], "next": "7799af8a0632c7898e09de3cfa60ffc938691aad" }