)]}'
{
  "commit": "8ce0278afc65fd3fd8a19e73c582a5dcd07c7d58",
  "tree": "0b67eed8de64145bd72b77f0c3b4b710a5fb24bd",
  "parents": [
    "10231090e5b59ff4ea6cf163f9b8b8b411b46a7c"
  ],
  "author": {
    "name": "Maxim Korotkov",
    "email": "korotkov.maxim.s@gmail.com",
    "time": "Mon Jul 20 12:18:52 2026"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jul 20 12:18:52 2026"
  },
  "message": "fix: assign unified L1 cache size to L1D (#180)\n\nIn the unified-cache fallback branch (cache type 3, neither Data nor\nInstruction), the code checked c.Cache.L1D \u003c 0 but assigned to L1I,\nleaving L1D at its -1 sentinel on CPUs reporting a unified L1 cache\nand setting L1I twice. Assign to L1D in that branch to match the\nguard. Applies to both the Intel and AMD/Hygon paths.\n\nFound by PostgresPro\n\nSigned-off-by: Maksim Korotkov \u003cm.korotkov@postgrespro.ru\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9aa6d25f92dc32804246cadb236917db9053802b",
      "old_mode": 33188,
      "old_path": "cpuid.go",
      "new_id": "741af8ac82d84f5643c08db2ad7718b18ee255fa",
      "new_mode": 33188,
      "new_path": "cpuid.go"
    }
  ]
}