HSD #15015934876: dts: socfpga_agilex5.dtsi: Fix the clk-csr for XGMAC
This patch is to to set the clk-csr divider value. The value is
set based on the clk_csr_i clock speed and currently the hardware
is connected with the l4_sp_clk (100MHz) thus the clk-csr divider
need to choose the divider with the value 62, due to that, the
csr-clk value need to choose divider option 0.
Signed-off-by: Boon Khai Ng <[email protected]>
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index d37b974..fd23576 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -235,6 +235,7 @@ gmac0: ethernet@10810000 {
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
altr,smtg-hub;
iommus = <&smmu 1>;
+ snps,clk-csr = <0>;
dma-coherent;
status = "disabled";
@@ -383,6 +384,7 @@ gmac1: ethernet@10820000 {
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
altr,smtg-hub;
iommus = <&smmu 2>;
+ snps,clk-csr = <0>;
dma-coherent;
status = "disabled";
@@ -531,6 +533,7 @@ gmac2: ethernet@10830000 {
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
altr,smtg-hub;
iommus = <&smmu 3>;
+ snps,clk-csr = <0>;
dma-coherent;
status = "disabled";
