| commit | e337b07a64e99a85190473debe84d49e10661930 | [log] [tgz] |
|---|---|---|
| author | Boon Khai Ng <[email protected]> | Wed May 08 03:19:51 2024 |
| committer | Boon Khai Ng <[email protected]> | Wed Jun 19 03:05:48 2024 |
| tree | 77f4ef16cc5e082598202f006c859b7ad29a7091 | |
| parent | 6b8857efd27e801c78145f9f490fa4499c4fb993 [diff] |
HSD #15015934876: dts: socfpga_agilex5.dtsi: Fix the clk-csr for XGMAC This patch is to to set the clk-csr divider value. The value is set based on the clk_csr_i clock speed and currently the hardware is connected with the l4_sp_clk (100MHz) thus the clk-csr divider need to choose the divider with the value 62, due to that, the csr-clk value need to choose divider option 0. Signed-off-by: Boon Khai Ng <[email protected]>