HSD #15011647732: arm64: dts: stratix10: update QSE driver DMA register map
Starting GHRD 21.4, Intel's Stratix10 SoCFPGA Quad Speed
Ethernet IP updated register mapping for Tx and Rx DMA related CSR
registers. This patch updates the QSE device tree with the new register
map to reflect the changes.
Signed-off-by: Teoh, Ji Sheng <[email protected]>
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
index c2a3238..c836307 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
@@ -30,11 +30,11 @@ s10_hps_bridges: bridge@80000000 {
<0x00000001 0x00020000 0xf9020000 0x00001000>,
<0x00000001 0x00022000 0xf9022000 0x00002000>,
<0x00000001 0x00026000 0xf9026000 0x00000040>,
- <0x00000001 0x00000420 0xf9000420 0x00000020>,
- <0x00000001 0x00000400 0xf9000400 0x00000020>,
- <0x00000001 0x00000520 0xf9000520 0x00000020>,
- <0x00000001 0x00000500 0xf9000500 0x00000020>,
- <0x00000001 0x00000540 0xf9000540 0x00000020>,
+ <0x00000001 0x00002020 0xf9002020 0x00000020>,
+ <0x00000001 0x00002000 0xf9002000 0x00000020>,
+ <0x00000001 0x00002120 0xf9002120 0x00000020>,
+ <0x00000001 0x00002100 0xf9002100 0x00000020>,
+ <0x00000001 0x00002140 0xf9002140 0x00000020>,
<0x00000001 0x00030100 0xf9030100 0x00000010>,
<0x00000001 0x00000300 0xf9000300 0x00000010>,
<0x00000001 0x00000310 0xf9000310 0x00000010>;
@@ -47,11 +47,11 @@ qse_0_qse: ethernet@0x100020000 {
reg = <0x00000001 0x00020000 0x00001000>,
<0x00000001 0x00022000 0x00002000>,
<0x00000001 0x00026000 0x00000040>,
- <0x00000001 0x00000420 0x00000020>,
- <0x00000001 0x00000400 0x00000020>,
- <0x00000001 0x00000520 0x00000020>,
- <0x00000001 0x00000500 0x00000020>,
- <0x00000001 0x00000540 0x00000020>,
+ <0x00000001 0x00002020 0x00000020>,
+ <0x00000001 0x00002000 0x00000020>,
+ <0x00000001 0x00002120 0x00000020>,
+ <0x00000001 0x00002100 0x00000020>,
+ <0x00000001 0x00002140 0x00000020>,
<0x00000001 0x00030100 0x00000010>;
dma-coherent;
phy-mode = "10gbase-r";
