JSTests/wasm/stress/simd-instructions-bitshift.js

//@ requireOptions("--useWasmSIMD=1")
//@ skip if !$isSIMDPlatform
import { runSIMDTests } from "./simd-instructions-lib.js"

const verbose = false;

// Each entry: [instruction, input0, input1, expected_output]
// Two test cases per instruction: shift < lane_width and shift >= lane_width
const bitshiftTests = [
    // i8x16 shift operations (lane width = 8 bits)
    [
        "i8x16.shl",
        [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0xFF, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01],
        "(i32.const 3)",
        [0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xF8, 0xF8, 0x78, 0x38, 0x18, 0x08]
    ],
    [
        "i8x16.shl",
        [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0xFF, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01],
        "(i32.const 11)",
        [0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xF8, 0xF8, 0x78, 0x38, 0x18, 0x08]
    ],
    
    [
        "i8x16.shr_s",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80],
        "(i32.const 2)",
        [0xE0, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0]
    ],
    [
        "i8x16.shr_s",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80],
        "(i32.const 8)",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80]
    ],
    
    [
        "i8x16.shr_u",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80],
        "(i32.const 2)",
        [0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00, 0x3F, 0x3F, 0x3F, 0x3E, 0x3C, 0x38, 0x30, 0x20]
    ],
    [
        "i8x16.shr_u",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80],
        "(i32.const 8)",
        [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0xFF, 0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80]
    ],

    // i16x8 shift operations (lane width = 16 bits)
    [
        "i16x8.shl",
        [0x0001, 0x0002, 0x0004, 0x0008, 0x8000, 0x4000, 0x2000, 0x1000],
        "(i32.const 4)",
        [0x0010, 0x0020, 0x0040, 0x0080, 0x0000, 0x0000, 0x0000, 0x0000]
    ],
    [
        "i16x8.shl",
        [0x0001, 0x0002, 0x0004, 0x0008, 0x8000, 0x4000, 0x2000, 0x1000],
        "(i32.const 16)",
        [0x0001, 0x0002, 0x0004, 0x0008, 0x8000, 0x4000, 0x2000, 0x1000]
    ],
    
    [
        "i16x8.shr_s",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100],
        "(i32.const 3)",
        [0xF000, 0x0800, 0x0400, 0x0200, 0x0100, 0x0080, 0x0040, 0x0020]
    ],
    [
        "i16x8.shr_s",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100],
        "(i32.const 16)",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100]
    ],
    
    [
        "i16x8.shr_u",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100],
        "(i32.const 3)",
        [0x1000, 0x0800, 0x0400, 0x0200, 0x0100, 0x0080, 0x0040, 0x0020]
    ],
    [
        "i16x8.shr_u",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100],
        "(i32.const 16)",
        [0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100]
    ],

    // i32x4 shift operations (lane width = 32 bits)
    [
        "i32x4.shl",
        [0x00000001, 0x00000002, 0x80000000, 0x40000000],
        "(i32.const 8)",
        [0x00000100, 0x00000200, 0x00000000, 0x00000000]
    ],
    [
        "i32x4.shl",
        [0x00000001, 0x00000002, 0x80000000, 0x40000000],
        "(i32.const 40)",
        [0x00000100, 0x00000200, 0x00000000, 0x00000000]
    ],
    
    [
        "i32x4.shr_s",
        [0x80000000, 0x40000000, 0x20000000, 0x10000000],
        "(i32.const 4)",
        [0xF8000000, 0x04000000, 0x02000000, 0x01000000]
    ],
    [
        "i32x4.shr_s",
        [0x80000000, 0x40000000, 0x20000000, 0x10000000],
        "(i32.const 32)",
        [0x80000000, 0x40000000, 0x20000000, 0x10000000]
    ],
    
    [
        "i32x4.shr_u",
        [0x80000000, 0x40000000, 0x20000000, 0x10000000],
        "(i32.const 4)",
        [0x08000000, 0x04000000, 0x02000000, 0x01000000]
    ],
    [
        "i32x4.shr_u",
        [0x80000000, 0x40000000, 0x20000000, 0x10000000],
        "(i32.const 36)",
        [0x08000000, 0x04000000, 0x02000000, 0x01000000]
    ],

    // i64x2 shift operations (lane width = 64 bits)
    [
        "i64x2.shl",
        [0x0000000000000001n, 0x8000000000000000n],
        "(i32.const 16)",
        [0x0000000000010000n, 0x0000000000000000n]
    ],
    [
        "i64x2.shl",
        [0x0000000000000001n, 0x8000000000000000n],
        "(i32.const 80)",
        [0x0000000000010000n, 0x0000000000000000n]
    ],
    
    [
        "i64x2.shr_s",
        [0x8000000000000000n, 0x4000000000000000n],
        "(i32.const 8)",
        [0xFF80000000000000n, 0x0040000000000000n]
    ],
    [
        "i64x2.shr_s",
        [0x8000000000000000n, 0x4000000000000000n],
        "(i32.const 64)",
        [0x8000000000000000n, 0x4000000000000000n]
    ],
    
    [
        "i64x2.shr_u",
        [0x8000000000000000n, 0x4000000000000000n],
        "(i32.const 8)",
        [0x0080000000000000n, 0x0040000000000000n]
    ],
    [
        "i64x2.shr_u",
        [0x8000000000000000n, 0x4000000000000000n],
        "(i32.const 64)",
        [0x8000000000000000n, 0x4000000000000000n]
    ]
];

await runSIMDTests(bitshiftTests, verbose, "SIMD bit shift");