)]}'
{
  "commit": "fb047130174be8ffad5718182ac83c2f5dcb45be",
  "tree": "1f5851614af279cd30ac3d79f5baa4e22bf15d0e",
  "parents": [
    "814c8e326ef778a4d1b51610dbf69e25e3db3701"
  ],
  "author": {
    "name": "aizu-m",
    "email": "aizumusheer2@gmail.com",
    "time": "Wed Jul 08 23:56:49 2026"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jul 08 23:56:49 2026"
  },
  "message": "Check memory64 addr+offset overflow in wasm2c store/atomic/simd ops (#2790)\n\nComparing wasm2c output either side of 4bedf7c (\"check address + offset\naddition for memory64\"):\n\n    // load  (fixed in 4bedf7c)\n    i64_load(\u0026M0, (u64)checked_add_u64(var_j0, 16u));\n    // store (still unchecked)\n    i64_store(\u0026M0, (u64)(var_j0) + 16, var_j1);\n\nThat commit only converted `CWriter::Write(const LoadExpr\u0026)`. For an i64\nmemory the store still adds the static offset with a wrapping `+`, and\nso do the SIMD lane/splat/zero and atomic emitters.\n\nHow I hit it: memory64 module, `i64.store offset\u003d16` at address\n`0xFFFFFFFFFFFFFFF0`. The sum overflows u64 to 0, the generated\n`RANGE_CHECK` sees an in-range address, and the write lands at guest\naddress 0. Per the spec that access should trap; the load form already\ndoes after 4bedf7c.\n\nApplied the same `checked_add_u64` guard to `StoreExpr`,\n`SimdLoadLaneExpr`, `SimdStoreLaneExpr`, `LoadSplatExpr`,\n`LoadZeroExpr`, `AtomicLoadExpr`, `AtomicStoreExpr`, `AtomicRmwExpr` and\n`AtomicRmwCmpxchgExpr` for `is_64` memories. The 32-bit output is byte\nfor byte unchanged. The wasm2c spec tests (memory64, threads, simd)\nstill pass.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2924451b0f9dce7c8de76ece013d2a061c5e570c",
      "old_mode": 33188,
      "old_path": "src/c-writer.cc",
      "new_id": "923397bf98d3cfbd86626882d3130693c9fc29b6",
      "new_mode": 33188,
      "new_path": "src/c-writer.cc"
    }
  ]
}