)]}' { "log": [ { "commit": "fbcd0c258b79b28c3c9282f309b6465d78f47003", "tree": "a8dba59b2b185a611b3f7f36e44e7a63e7e2b859", "parents": [ "a927efb0309db45c072a875e56f750b1be65ec44" ], "author": { "name": "Nitika Achra", "email": "nitachra@amd.com", "time": "Mon May 11 14:52:49 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jun 02 06:54:11 2026" }, "message": "add AMD Zen6 (Fam 1Ah) L3 PMU support\n\nAdd a new PMU model: amd64_fam1ah_zen6_l3, with the 3 currently\npublished L3 events.\n\nBased on the publicly available \"Performance Monitor Counters for AMD\nFamily 1Ah Model 50h-57h Processors\", rev 1.00:\n\n https://docs.amd.com/v/u/en-US/69163-VenicePMC-pub\n\nSigned-off-by: Swarup Sahoo \u003cswarup-chandra.sahoo@amd.com\u003e\nSigned-off-by: Nitika Achra \u003cnitachra@amd.com\u003e\n" }, { "commit": "a927efb0309db45c072a875e56f750b1be65ec44", "tree": "8bb71d91ae453a57f4aef0aa1f051ad82026169d", "parents": [ "b6de644ecfa4627f87726292f2638663c23a2f63" ], "author": { "name": "Nitika Achra", "email": "nitachra@amd.com", "time": "Mon May 11 14:52:15 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jun 02 06:24:46 2026" }, "message": "add AMD Zen6 (Fam 1Ah) core PMU support\n\nAdd a new PMU model: amd64_fam1ah_zen6.\n\nBased on the publicly available \"Performance Monitor Counters for AMD\nFamily 1Ah Model 50h-57h Processors\", rev 1.00:\n\n https://docs.amd.com/v/u/en-US/69163-VenicePMC-pub\n\nSigned-off-by: Swarup Sahoo \u003cswarup-chandra.sahoo@amd.com\u003e\nSigned-off-by: Nitika Achra \u003cnitachra@amd.com\u003e\n" }, { "commit": "b6de644ecfa4627f87726292f2638663c23a2f63", "tree": "0347bf1ae35cdf8c8d5c6a8d2a62807866b338b2", "parents": [ "d89aa86628073d55a2234ba15064f138b8fe4370" ], "author": { "name": "Nitika Achra", "email": "nitachra@amd.com", "time": "Wed May 27 07:59:41 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri May 29 05:07:28 2026" }, "message": "amd64: drop unused amd64_fam1ah_zen5_retired_serializing_ops table\n\nThe amd64_fam1ah_zen5_retired_serializing_ops[] umask table is defined\nin lib/events/amd64_events_fam1ah_zen5.h but is not referenced by any\nevent entry in amd64_fam1ah_zen5_pe[]. It is dead code that was added\ntogether with the initial Zen5 support and has never been wired up.\n\nNo functional change.\n\nSigned-off-by: Swarup Sahoo \u003cswarup-chandra.sahoo@amd.com\u003e\nSigned-off-by: Nitika Achra \u003cnitachra@amd.com\u003e\n" }, { "commit": "d89aa86628073d55a2234ba15064f138b8fe4370", "tree": "af68479fc07efcb7a065c9b6de51ae1ed271075d", "parents": [ "977a25bb3dfe45f653a6cee71ffaae9a92fc3095" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri May 29 04:58:49 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri May 29 04:59:46 2026" }, "message": "add basic support for JSON output\n\nAdds the -j option to print the basic event information in JSON format.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "977a25bb3dfe45f653a6cee71ffaae9a92fc3095", "tree": "1025d67a85ed37e06c890eaca527cbfa17c708cc", "parents": [ "1b0d0d3bfd375dbb659cad0572f0f2086e016549" ], "author": { "name": "Thomas Makin", "email": "tmakin@nvidia.com", "time": "Thu Jan 29 17:34:16 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Mar 28 07:07:50 2026" }, "message": "perf_examples: update task_cpu max cpus to 512\n\nIncrease the maximum number of CPUS supported to\naccommodate larger servers.\n\nSigned-off-by: Thomas Makin \u003ctmakin@nvidia.com\u003e\n" }, { "commit": "1b0d0d3bfd375dbb659cad0572f0f2086e016549", "tree": "c526a96077b252edc44ebb2338ecd103ccba5c5f", "parents": [ "41878eab48c50bb9ec5f741a013e971bb5a9dff2" ], "author": { "name": "Thomas Makin", "email": "tmakin@nvidia.com", "time": "Thu Nov 13 15:44:43 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Mar 28 06:59:43 2026" }, "message": "perf/arm: add NVIDIA Olympus support\n\nOlympus is an ARMv9.2 core used in the NVIDIA Tegra410 SoC.\nThis change adds support for the Olympus Core PMU.\n\nBased on source code available from:\nhttps://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/commit/?h\u003dperf-tools-next\u0026id\u003d86ff690f45cc034ab32246630b3c7d7a46d1ae6b\n\nSigned-off-by: Thomas Makin \u003ctmakin@nvidia.com\u003e\n" }, { "commit": "41878eab48c50bb9ec5f741a013e971bb5a9dff2", "tree": "8cfd9434d9f97cb3ff936f5f234db5b6ee0d0292", "parents": [ "5a3f140150cd63adffb95c7c6d59381229a6b767" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Mar 25 04:44:51 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Mar 25 04:44:51 2026" }, "message": "Fix validation error for ARM Cortex X4 BR_RET_SPEC\n\nLine 512, Event66 arm_x4::BR_RET_SPEC, ret\u003devent not found(-4) expected success(0)\n\nBecause the event is actuall BR_RETURN_SPEC.\nPatch fixes the typo\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "5a3f140150cd63adffb95c7c6d59381229a6b767", "tree": "1c1e40e3011bf4b4f965d5c6d0abb6a2e27843a8", "parents": [ "4d6a907932a2273e23ef578cda68e154c0eeda3b" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 13 06:55:45 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 13 06:55:45 2026" }, "message": "updated Intel SPR support\n\nUpdate to Intel SPR github repo v1.38\n\ngithub.com/Intel/perfmon/SPR/events/sapphirerapids_core.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "4d6a907932a2273e23ef578cda68e154c0eeda3b", "tree": "4e69f9d41ddddf784f132b52816875b387016af8", "parents": [ "86a9dc23f62ea14651dbe22b58211747f9f3d8fe" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Mar 12 03:37:01 2026" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Mar 12 03:37:01 2026" }, "message": "fix Intel Icelake MEM_LOAD_MISC_RETIRED event code\n\nWas set to 0xc4 instead of 0xd4\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "86a9dc23f62ea14651dbe22b58211747f9f3d8fe", "tree": "dec0638dd2034268b5c0fa018d42e6bae0e474c6", "parents": [ "964baf9d35d5f88d8422f96d8a82c672042e7064" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Oct 02 04:09:17 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Oct 03 03:45:29 2025" }, "message": "add support for ARM Cortex X4 core PMU\n\nAdds ARM Cortex X4 core PMU support.\nBased on:\n https://github.com/ARM-software/data/blob/master/pmu/cortex-x4.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "964baf9d35d5f88d8422f96d8a82c672042e7064", "tree": "cb91412ed6d1394d18a1a3ff07f77be08790b760", "parents": [ "3e4031b2ddc555c8178c813925eb5f6872e2daa8" ], "author": { "name": "Thomas Richter", "email": "tmricht@linux.ibm.com", "time": "Tue Jun 18 09:56:18 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Aug 26 04:42:20 2025" }, "message": "s390: Add counter definition for IBM z17\n\nAdd the libpfm4 s390 counter definitions for IBM z17 according\nto documentation:\n\nSA23-2261-09:The CPU-Measurement Facility Extended Counters\n Definition for z10, z196/z114, zEC12/zBC12, z13/z13s,\n z14, z15, z16 and z17\n April 2025\n\nhttps://www.ibm.com/docs/en/module_1678991624569/pdf/SA23-2261-09.pdf\n\nSigned-off-by: Thomas Richter \u003ctmricht@linux.ibm.com\u003e\n" }, { "commit": "3e4031b2ddc555c8178c813925eb5f6872e2daa8", "tree": "789af1fa87db609bc53a537a151e0acf9c9aaf2d", "parents": [ "7c827e3ed260e151881d7825064b1df45629557c", "861ce2a29b214ce182e105f428f55cdc2ed51af1" ], "author": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Jun 29 01:32:07 2025" }, "committer": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Jun 29 01:32:07 2025" }, "message": "Merge /u/kotaro-tokai/perfmon2/ branch monaka-v1.1-support into master\n\nhttps://sourceforge.net/p/perfmon2/libpfm4/merge-requests/35/\n" }, { "commit": "7c827e3ed260e151881d7825064b1df45629557c", "tree": "3beff7b71e84ea097689fea3e60d6bf9d33102e3", "parents": [ "0727e5f5561101d8c635a36e139dd7512616d49e", "4086140e2041bf6403d0f9c4309c2de920386f47" ], "author": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Jun 29 01:20:46 2025" }, "committer": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Jun 29 01:20:46 2025" }, "message": "Merge /u/tmalesinski/perfmon2/ branch python3-fix into master\n\nhttps://sourceforge.net/p/perfmon2/libpfm4/merge-requests/33/\n" }, { "commit": "861ce2a29b214ce182e105f428f55cdc2ed51af1", "tree": "743f630356650da86104110a273eca9868a2ccd4", "parents": [ "0727e5f5561101d8c635a36e139dd7512616d49e" ], "author": { "name": "Kotaro, Tokai", "email": "fj0635gf@aa.jp.fujitsu.com", "time": "Wed Jun 18 03:01:43 2025" }, "committer": { "name": "Kotaro, Tokai", "email": "fj0635gf@aa.jp.fujitsu.com", "time": "Wed Jun 18 03:01:43 2025" }, "message": "The FUJITSU-MONAKA PMU events have been changed to match the v1.1 specification and v1.0 errata.\n\nFUJITSU-MONAKA Specification URL:\nhttps://github.com/fujitsu/FUJITSU-MONAKA\n\nThe changed events are as follows:\n\nRemoved events:\n\n- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT\n\nAdded events:\n\n- ASE_FP_VREDUCE_SPEC\n- SVE_FP_PREDUCE_SPEC\n- ASE_FP_BF16_MIN_SPEC\n- ASE_FP_FP8_MIN_SPEC\n- ASE_SVE_FP_BF16_MIN_SPEC\n- ASE_SVE_FP_FP8_MIN_SPEC\n- SVE_FP_BF16_MIN_SPEC\n- SVE_FP_FP8_MIN_SPEC\n- FP_BF16_MIN_SPEC\n- FP_FP8_MIN_SPEC\n- FP_BF16_FIXED_MIN_OPS_SPEC\n- FP_FP8_FIXED_MIN_OPS_SPEC\n- FP_BF16_SCALE_MIN_OPS_SPEC\n- FP_FP8_SCALE_MIN_OPS_SPEC\n\nRenamed events:\n\n- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT\n- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT\n- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT\n- L2D_CACHE_REFILL_L3D_MISS_L_MEM \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM\n- L2D_CACHE_REFILL_L3D_MISS_FR_MEM \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM\n- L2D_CACHE_REFILL_L3D_MISS_L_L2 \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_L_L2\n- L2D_CACHE_REFILL_L3D_MISS_NR_L2 \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2\n- L2D_CACHE_REFILL_L3D_MISS_NR_L3 \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3\n- L2D_CACHE_REFILL_L3D_MISS_FR_L2 \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2\n- L2D_CACHE_REFILL_L3D_MISS_FR_L3 \u003d\u003e L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3\n\nDescription changed events:\n\n- STALL_BACKEND\n- LL_CACHE_MISS_RD\n- L2D_CACHE_RD\n- L2D_CACHE_WR\n- L2D_CACHE_REFILL_RD\n- L2D_CACHE_REFILL_WR\n- CSDB_SPEC\n- EXC_SMC\n- FP_MV_SPEC\n- IEL_SPEC\n- IREG_SPEC\n- BC_LD_SPEC\n- LD_COMP_WAIT\n- LD_COMP_WAIT_EX\n- L1_PIPE_COMP_GATHER_2FLOW\n- L1_PIPE_COMP_GATHER_1FLOW\n- L1_PIPE_COMP_GATHER_0FLOW\n- L2D_CACHE_HWPRF_ADJACENT\n- L2D_CACHE_REFILL_L3D_CACHE_PRF\n- L2D_CACHE_REFILL_L3D_CACHE_HWPRF\n- L2D_CACHE_REFILL_L3D_MISS_PRF\n- L2D_CACHE_REFILL_L3D_MISS_HWPRF\n- L2D_CACHE_REFILL_L3D_HIT_PRF\n- L2D_CACHE_REFILL_L3D_HIT_HWPRF\n- L1I_TLB_REFILL_4K\n- L1I_TLB_REFILL_64K\n- L1I_TLB_REFILL_2M\n- L1I_TLB_REFILL_32M\n- L1I_TLB_REFILL_512M\n- L1I_TLB_REFILL_1G\n- L1I_TLB_REFILL_16G\n- L1D_TLB_REFILL_4K\n- L1D_TLB_REFILL_64K\n- L1D_TLB_REFILL_2M\n- L1D_TLB_REFILL_32M\n- L1D_TLB_REFILL_512M\n- L1D_TLB_REFILL_1G\n- L1D_TLB_REFILL_16G\n- L2I_TLB_REFILL_4K\n- L2I_TLB_REFILL_64K\n- L2I_TLB_REFILL_2M\n- L2I_TLB_REFILL_32M\n- L2I_TLB_REFILL_512M\n- L2I_TLB_REFILL_1G\n- L2I_TLB_REFILL_16G\n- L2D_TLB_REFILL_4K\n- L2D_TLB_REFILL_64K\n- L2D_TLB_REFILL_2M\n- L2D_TLB_REFILL_32M\n- L2D_TLB_REFILL_512M\n- L2D_TLB_REFILL_1G\n- L2D_TLB_REFILL_16G\n- L2D_CACHE_LMISS_RD\n- L3D_CACHE_LMISS_RD\n- ASE_INST_SPEC\n- ASE_SVE_INST_SPEC\n- UOP_SPEC\n- ASE_SVE_FP_SPEC\n- ASE_SVE_FP_HP_SPEC\n- ASE_SVE_FP_SP_SPEC\n- ASE_SVE_FP_DP_SPEC\n- ASE_SVE_FP_DIV_SPEC\n- ASE_SVE_FP_SQRT_SPEC\n- FP_FMA_SPEC\n- ASE_SVE_FP_FMA_SPEC\n- FP_MUL_SPEC\n- ASE_SVE_FP_MUL_SPEC\n- FP_ADDSUB_SPEC\n- ASE_SVE_FP_ADDSUB_SPEC\n- ASE_FP_RECPE_SPEC\n- SVE_FP_RECPE_SPEC\n- ASE_SVE_FP_RECPE_SPEC\n- ASE_SVE_FP_CVT_SPEC\n- SVE_FP_AREDUCE_SPEC\n- ASE_FP_PREDUCE_SPEC\n- ASE_SVE_FP_VREDUCE_SPEC\n- ASE_INT_SPEC\n- SVE_INT_SPEC\n- ASE_SVE_INT_SPEC\n- ASE_SVE_INT_MUL_SPEC\n- SVE_INT_MULH64_SPEC\n- NONFP_SPEC\n- ASE_NONFP_SPEC\n- SVE_NONFP_SPEC\n- ASE_SVE_NONFP_SPEC\n- ASE_SVE_INT_VREDUCE_SPEC\n- ASE_SVE_LD_SPEC\n- ASE_SVE_ST_SPEC\n- ASE_SVE_LD_MULTI_SPEC\n- ASE_SVE_ST_MULTI_SPEC\n- FP_SCALE_OPS_SPEC\n- FP_FIXED_OPS_SPEC\n- FP_HP_SCALE_OPS_SPEC\n- FP_HP_FIXED_OPS_SPEC\n- FP_SP_SCALE_OPS_SPEC\n- FP_SP_FIXED_OPS_SPEC\n- FP_DP_SCALE_OPS_SPEC\n- FP_DP_FIXED_OPS_SPEC\n- L1I_CACHE_HWPRF\n- L1D_CACHE_HWPRF\n- L2D_CACHE_HWPRF\n- STALL_BACKEND_L2D\n- L1I_CACHE_REFILL_HWPRF\n- L1D_CACHE_REFILL_HWPRF\n- L2D_CACHE_REFILL_HWPRF\n- L2D_CACHE_HIT_RD\n- L2D_CACHE_HIT_WR\n- L2D_CACHE_HIT\n- L1I_CACHE_PRF\n- L1D_CACHE_PRF\n- L2D_CACHE_PRF\n- L1I_CACHE_REFILL_PRF\n- L1D_CACHE_REFILL_PRF\n- L2D_CACHE_REFILL_PRF\n- L1D_CACHE_REFILL_PERCYC\n- L2D_CACHE_REFILL_PERCYC\n- L1I_CACHE_REFILL_PERCYC\n\nSigned-off-by: Kotaro, Tokai \u003cfj0635gf@aa.jp.fujitsu.com\u003e\n" }, { "commit": "0727e5f5561101d8c635a36e139dd7512616d49e", "tree": "15d5233805c3614b16a88adcf5ca58714c4bf160", "parents": [ "75d2e605f763f3220793c3bb52a6b6effffe4d9c" ], "author": { "name": "Vince Weaver", "email": "vincent.weaver@maine.edu", "time": "Sat May 24 00:32:23 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat May 24 00:32:23 2025" }, "message": "add another perf_name for ARM Cortex-A57\n\nPAPI developers with NVIDIA Jetson board and ARM Cortex-A57\nreported that the Linux PMU type is \"armv8_pmuv3\"\nAdd that name as a possible name to the list of perf_name\nfor Cortex A57.\n\nSigned-off-by: Vince Weaver \u003cvincent.weaver@maine.edu\u003e\n" }, { "commit": "75d2e605f763f3220793c3bb52a6b6effffe4d9c", "tree": "0a3097494c520bcfca2ab1f4def8eaf6f5d815f0", "parents": [ "c5587f9931123be6fcb6f8133497d93cab36bdcd" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri May 16 04:53:17 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri May 16 05:02:32 2025" }, "message": "fix AMD Zen5 umasks for L2_PREFETCH_MISS_L3 and L2_FILL_RESPONSE_SRC\n\nThe umasks tables were swapped between the two events.\nSimplify umasks names for L2_FILL_RESPONSE_SRC\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "4086140e2041bf6403d0f9c4309c2de920386f47", "tree": "d06f62b46fe8cd4e31f07a6adfa3c0cf7c152601", "parents": [ "dd015ac9f0e8eedba3c28d60e43bde47f969db78" ], "author": { "name": "Tomek Malesinski", "email": "tmalesinski@gmail.com", "time": "Sun Apr 27 10:43:31 2025" }, "committer": { "name": "Tomek Malesinski", "email": "tmalesinski@gmail.com", "time": "Sun Apr 27 10:43:31 2025" }, "message": "Modernize setup.py slightly.\n\nFollowing:\nhttps://packaging.python.org/en/latest/guides/modernize-setup-py-project/\n" }, { "commit": "dd015ac9f0e8eedba3c28d60e43bde47f969db78", "tree": "545fa5a93482524a6368ba8e5c544fa68b18024f", "parents": [ "c5587f9931123be6fcb6f8133497d93cab36bdcd" ], "author": { "name": "Tomek Malesinski", "email": "tmalesinski@gmail.com", "time": "Sun Apr 27 10:42:26 2025" }, "committer": { "name": "Tomek Malesinski", "email": "tmalesinski@gmail.com", "time": "Sun Apr 27 10:42:26 2025" }, "message": "Use relative imports according to PEP 328\n" }, { "commit": "c5587f9931123be6fcb6f8133497d93cab36bdcd", "tree": "d2c54b217aeec411f31ed781d4dcfe89b4741d4a", "parents": [ "b2888ea7995d781d1c59d9c8714487b863774912" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 21 18:03:41 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 21 18:06:52 2025" }, "message": "Hotfix ARM CPU detection due to arch mismatch\n\nThis is a hotfix to avoid failure of ARM CPU detection with the new\ndetection code introduce by commit 15c4cd9f1f4a (\"Add ARM hybrid detection\").\n\nFor some processors, the architecture revision expected by libpfm4 does not\nmatch the revision exported by the Linux kernel via cpuinfo. For instance,\nthe Neoverse V2 is a V9 processor, yet cpuinfo reports arch: 8. A few other\nARM processors may exhibit the same error.\n\nThe hotfix simply skips checking the arch revision for now.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "b2888ea7995d781d1c59d9c8714487b863774912", "tree": "288e33ea644c80b65811de012867a31f4a1d8e63", "parents": [ "f09c366b45fba75f1143cb14ec8f22ad96c4c1b1" ], "author": { "name": "Samuel Thibault", "email": "samuel.thibault@ens-lyon.org", "time": "Sun Mar 09 06:54:04 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Mar 09 06:54:04 2025" }, "message": "Cope with empty /proc/cpuinfo file\n\nWhen running inside e.g. lxc containers, /proc/cpuinfo may be empty, in\nwhich case pfmlib_getl() never allocates a buffer, and the trailing b[i] \u003d\n\u0027\\0\u0027 thus becomes bogus.\n\nSigned-off-by: Samuel Thibault \u003csamuel.thibault@ens-lyon.org\u003e\n" }, { "commit": "f09c366b45fba75f1143cb14ec8f22ad96c4c1b1", "tree": "876c30f174d7a84ef9444119a7231e49f5203c1c", "parents": [ "e887d24a6c4b97b8087e5a284c79f63adaab4fc0", "8ca3087c05480e7f3368f558665d3b13b742929a" ], "author": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Mar 09 06:27:13 2025" }, "committer": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Sun Mar 09 06:27:13 2025" }, "message": "Merge /u/mousezhang/perfmon2/ branch master into master\n\nhttps://sourceforge.net/p/perfmon2/libpfm4/merge-requests/32/\n" }, { "commit": "e887d24a6c4b97b8087e5a284c79f63adaab4fc0", "tree": "02bf8fdc8445a24ea6d2f31deef4ecfd41b39e6f", "parents": [ "ff3291fe3f6d2c280ed2e33c42842e5dc08f38df" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Sep 26 16:38:50 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Mar 09 05:38:15 2025" }, "message": "Add sysfs PMU caching on initialization\n\nIn order to accommodate the growing number of PMUs active and to\nhandle hybrid processors better, this patch adds sysfs PMU perf_events\ninformation caching to avoid going back to sysfs for each encoded event.\nThe caching stores the name of PMU, e.g., armv8_pmu3, and the perf_events\ntype which is then use to build the perf_events encoding.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "ff3291fe3f6d2c280ed2e33c42842e5dc08f38df", "tree": "332b524a7bf47ab5dfca49bd75ec788d4ae8917c", "parents": [ "a41f8eeedf2c81232e5fa9129928edf9215bf3fc" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 00:35:37 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Mar 09 05:37:37 2025" }, "message": "Remove references to /sys/devices to remain compatible with upstream\n\nThe PMUs will not appear in /sys/devices for much longer.\nThe proper way to access PMU directories is via:\n/sys/bus/event_source/devices/\n\nWhere each PMU has a symlink.\n\nIt should be noted that this alternate directory is not new. It has\nbeen there all along. Therefore it is okay to remove all references\nto /sys/devices.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "a41f8eeedf2c81232e5fa9129928edf9215bf3fc", "tree": "884d7b0573253d5593823abb56f246dac0a8034c", "parents": [ "15c4cd9f1f4a382ef6753a05a5d4d6c27bd449c5" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Sep 18 18:05:44 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Mar 09 05:35:15 2025" }, "message": "Add ARM hybrid encoding support for perf_events\n\nThis patch adds the new logic to handle encoding of the PMU type\nfor the Linux perf_events interface. Hybrids are a challenge\nin that it is not possible to simply use PERF_TYPE_RAW because\nthat does not disambiguate which of the core PMU models to attach\nthe events to. Instead, the PMU type must be collected from the\nLinux sysfs interface. But for that to happen the library needs\nto know the PMU instance name assigned by perf_events for each\nPMU model detected. On ARM, this is not straightforward.\n\nThe patch extends the meaning the the pmu-\u003eperf_name string to include\na comma separated list of names instead of just one. The library then\ntries each name until there is a match in /sys/bus/event_source/devices/.\nThis accommodates situations where the same PMU model is used in a\nhomogeneous vs. hybrid config.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "15c4cd9f1f4a382ef6753a05a5d4d6c27bd449c5", "tree": "a45cdf9b6e4d520462d90f9ac0676b2f68d0a092", "parents": [ "762ca94010d9a8f21f0440c0b5807e9a2e849420" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 20 06:41:22 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Mar 09 05:34:19 2025" }, "message": "Add ARM hybrid detection\n\nThis patch rewrites the ARM core PMU detection logic\nto handle the case of hybrid processors. On ARM, there\ncan be many different cores in the same SoC. Each\npotentially shows up with a different implementer, part, variant.\nThat means just looking at the first entry in cpuinfo on Linux\nis not enough to activate all supported event tables.\n\nThe new code parses the entire cpuinfo once and detects each\nunique core identifiers. Then, for each core PMU table, the detection\ncode checks against that pre-built list of detected core models.\nThat way up to N (currently 8) different core models can be detected.\n\nThis new detection code is provided for Linux. For other operating\nsystems, new code must be added to get the implementer, part, variant\ncodes for all cores in the system.\n\nThanks to Vince Weaver for providing the test cases to exercise this\nnew code.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "8ca3087c05480e7f3368f558665d3b13b742929a", "tree": "6ed4e734007093e477b828c7b062ed98b405fab0", "parents": [ "762ca94010d9a8f21f0440c0b5807e9a2e849420" ], "author": { "name": "Mouse Zhang", "email": "mousezhang7@gmail.com", "time": "Thu Mar 06 12:35:40 2025" }, "committer": { "name": "Mouse Zhang", "email": "mousezhang7@gmail.com", "time": "Thu Mar 06 12:35:40 2025" }, "message": "fix typo Kinghts -\u003e Knights\n" }, { "commit": "762ca94010d9a8f21f0440c0b5807e9a2e849420", "tree": "064c84b138e3572578cd15a10d9ec5f9343078d7", "parents": [ "66627c778115b7d5a1cd6200250b7c4b07bccc67" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Oct 19 22:34:10 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 05:42:49 2025" }, "message": "Cleanup Alderlake event descriptions\n\nRemove . at end of descriptions.\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "66627c778115b7d5a1cd6200250b7c4b07bccc67", "tree": "2864bbbfbd0d402e1fb8312cba386063490c499a", "parents": [ "59aae0f5ce1dda4013063a4d192ab793179916d6" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 04:52:37 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 05:42:49 2025" }, "message": "Add Intel GraniteRapids uncore IMC PMU support\n\nAdds Intel GraniteRapids uncore IMC (memory controller) PMU support.\n - Based on Intel JSON event table version : 1.06\n - Based on Intel JSON event table published : 01/17/2025\n\nAvailable at github.com/Intel/perfmon\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "59aae0f5ce1dda4013063a4d192ab793179916d6", "tree": "dfe8b8179e6fd9ff4391742003df8991fc7653f7", "parents": [ "876528e6213b478986ba2fef768ee7e06df0e5fd" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 01:04:11 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 01:06:25 2025" }, "message": "Fix clang unused function/variable errors\n\nWith clang and -Werrors, the library did not compile.\nFix both issues:\n\t- unused perf_get_ovfl_umask_idx() with CONFIG_PFMLIB_NOTRACEPOINT set\n\t- unused variable sum in self_smpl_multi.c\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "876528e6213b478986ba2fef768ee7e06df0e5fd", "tree": "0ce5f0c78d765a03dd882df17dae406ab52e1fa1", "parents": [ "7750d00833a607eeb53c9a6832ffa8a6b827cdb9" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 00:07:40 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Feb 10 00:07:40 2025" }, "message": "Update Intel GraniteRapids core events to 1.06\n\nUpdates the Intel GraniteRapids core PMU event table\nto latest Intel released version:\n\nDate : 01/17/2025\nVersion: 1.06\n\nFrom gitub.com/Intel/perfmon\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "7750d00833a607eeb53c9a6832ffa8a6b827cdb9", "tree": "3700001830de331a7e1c8a0584933bd9c6e919b6", "parents": [ "d22403ec9bddaf62c59d847904918b30db69550d" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jan 28 00:35:05 2025" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jan 28 00:35:05 2025" }, "message": "fix AMD Zen5 encodings for L2_FILL_RESPONSE_SRC and L2_PREFETCH_MISS_L3\n\nEvent codes were swapped.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "d22403ec9bddaf62c59d847904918b30db69550d", "tree": "71b8b718f525510025c61a60f230b14028768374", "parents": [ "0003418f8b698cbb2709e7f6931c6fd94e634f98" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Dec 13 08:42:42 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Dec 13 08:42:42 2024" }, "message": "make L1I_CACHE_ACCESS an alias to the official L1I_CACHE event\n\nCovers Neoverse N1, N2, N3, V1, V2.\nL1I_CACHE_ACCESS is marked as deprecated.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "0003418f8b698cbb2709e7f6931c6fd94e634f98", "tree": "891f73a0d16db92d3319ed306ade884e9a850350", "parents": [ "5e26b48b6d9b9d5f8c368c81cfe23a54a129bd24" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Dec 13 08:23:03 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Dec 13 08:23:03 2024" }, "message": "update perf_events interface header to 6.12\n\nUpdate perf_event.h to reflect state in 6.12.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "5e26b48b6d9b9d5f8c368c81cfe23a54a129bd24", "tree": "d1959be934e2c01b899c6c4adc3816be52e1cf4f", "parents": [ "91970fe6eb4e80b63f77fb54a9592e28a207050c" ], "author": { "name": "Yoshihiro Furudera", "email": "fj5100bi@fujitsu.com", "time": "Thu Oct 03 07:25:55 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Nov 25 01:18:41 2024" }, "message": "Enable support for FUJITSU-MONAKA core PMU\n\nThis patch adds support for FUJITSU-MONAKA core PMU. This\nincludes ARMv9 generic core events and FUJITSU-MONAKA\nspecfic events.\n\nFUJITSU-MONAKA Specification URL:\nhttps://github.com/fujitsu/FUJITSU-MONAKA\n\nSigned-off-by: Yoshihiro Furudera \u003cfj5100bi@fujitsu.com\u003e\n" }, { "commit": "91970fe6eb4e80b63f77fb54a9592e28a207050c", "tree": "eb8b7a279f76e09da49c158dbc2be49d55bd936b", "parents": [ "1c2c67b38cd28823b3e34208b86e4656b55d310f" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Oct 05 04:49:47 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Oct 06 19:43:18 2024" }, "message": "Add ARM Neoverse N3 core PMU support\n\n Adds ARM Neoverse N3 core PMU support.\n Based on:\n https://github.com/ARM-software/data/blob/master/pmu/neoverse-n3.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "1c2c67b38cd28823b3e34208b86e4656b55d310f", "tree": "3f641d94a0fb275984590f807cfa1382f43f0e1b", "parents": [ "298127beb46c43ed02f8d2f8efc8ce52a9d601db" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Oct 04 05:18:54 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Oct 04 05:18:54 2024" }, "message": "fix group_pmu initialization in perf_examples/task\n\nVariable was reinitialized at each iteration preventing\nevents from being group by fd via perf_event_open()\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "298127beb46c43ed02f8d2f8efc8ce52a9d601db", "tree": "8c69be0ff350d662a5c8dc1cb00da120033f3376", "parents": [ "d01108b9b470131545389be4f2f479d0fa4b9444" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:36:23 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:43:14 2024" }, "message": "Add support for Topdown via PERF_METRICS for Intel Icelake/IcelakeX\n\nAdd the TOPDOWN_M dedicated event to provide the pseudo\nencodings necessary to program Topdown L1 events onto the\nPERF_METRICS MSR of Intel GraniteRapids on Linux.\n\nIn order to successfully use PERF_METRICS, the kernel imposes\nsome restrictions (which are not known to libpfm4) which the\nuser must follow:\n TOPDOWN_M events must be passed to the kernel in a single\n perf_events group (chained fds) AND the TOPDOWN_M.SLOTS event\n must be the first event in that group.\n\nNote that only the SLOTS events (programmed in fixed counter3)\nsupport modifiers such as user vs. kernel, hw_smpl or precise\nsampling on perf_events. All other umasks do not support any modifier.\nThe SLOTS event controls the filtering for all PERF_METRICS pseudo\nevents.\n\nThe encodings provided by libpfm4 for fixed counters are specific\nto Linux. When used on non Linux systems, encodings are not\nguaranteed to be valid.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "d01108b9b470131545389be4f2f479d0fa4b9444", "tree": "4a6cf381ecf49708483cce66488357dfcee459e4", "parents": [ "d9de389d9cf168116b4753ac7d94edbffcd2a161" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:26:40 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:43:14 2024" }, "message": "Add support for Topdown via PERF_METRICS for Intel GraniteRapids\n\nCut \u0026 paste of the Intel SapphireRapids support.\n\nAdd the TOPDOWN_M dedicated event to provide the pseudo\nencodings necessary to program Topdown L1 and L2 events onto the\nPERF_METRICS MSR of Intel GraniteRapids on Linux.\n\nIn order to successfully use PERF_METRICS, the kernel imposes\nsome restrictions (which are not known to libpfm4) which the\nuser must follow:\n TOPDOWN_M events must be passed to the kernel in a single\n perf_events group (chained fds) AND the TOPDOWN_M.SLOTS event\n must be the first event in that group.\n\nNote that only the SLOTS events (programmed in fixed counter3)\nsupport modifiers such as user vs. kernel, hw_smpl or precise\nsampling on perf_events. All other umasks do not support any modifier.\nThe SLOTS event controls the filtering for all PERF_METRICS pseudo\nevents.\n\nThe encodings provided by libpfm4 for fixed counters are specific\nto Linux. When used on non Linux systems, encodings are not\nguaranteed to be valid.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "d9de389d9cf168116b4753ac7d94edbffcd2a161", "tree": "be1dde02f84bc20dd4a0a37c868cb63bf4d73bfd", "parents": [ "1530567c76d290233b68e71b064cb1c3abfde8c3" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Aug 23 06:36:03 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:43:14 2024" }, "message": "Add support for Topdown via PERF_METRICS for Intel SapphireRapids\n\nAdd the TOPDOWN_M dedicated event to provide the pseudo\nencodings necessary to program Topdown L1 and L2 events onto the\nPERF_METRICS MSR of Intel SapphireRapids on Linux.\n\nIn order to successfully use PERF_METRICS, the kernel imposes\nsome restrictions (which are not known to libpfm4) which the\nuser must follow:\n TOPDOWN_M events must be passed to the kernel in a single\n perf_events group (chained fds) AND the TOPDOWN_M.SLOTS event\n must be the first event in that group.\n\nNote that only the SLOTS events (programmed in fixed counter3)\nsupport modifiers such as user vs. kernel, hw_smpl or precise\nsampling on perf_events. All other umasks do not support any modifier.\nThe SLOTS event controls the filtering for all PERF_METRICS pseudo\nevents.\n\nThe encodings provided by libpfm4 for fixed counters are specific\nto Linux. When used on non Linux systems, encodings are not\nguaranteed to be valid.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "1530567c76d290233b68e71b064cb1c3abfde8c3", "tree": "d5f69f5be7b3d03569f32fd1b6c352c2ffe2de53", "parents": [ "7e131752c0e486555cbb57342cdac2087e129dd4" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:35:15 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:43:14 2024" }, "message": "add support_no_mods support to Intel X86 encoding\n\nThis patch adds support for attribute info support_no_mods\nto Intel X86 encoding routines. There is a new INTEL_X86_NO_MODS\nflags that can be set on umasks flags field.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "7e131752c0e486555cbb57342cdac2087e129dd4", "tree": "a48373e635118cb3af1ccdd56627eb975188885d", "parents": [ "bf495f91ef5c455af0de679703090566a776b65a" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:11:41 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 05:41:30 2024" }, "message": "Add support_no_mods support to perf_events encoding\n\nThis patch adds handling of the support_no_mods attribute info to\nperf_events encoding routine. If the flag is set for any umasks\nthen it is applied to all. It is expected that events with such\nconditions prohibit umasks combinations. Only the perf_events\npinned attribute is maintained because it is a modifier of the\nperf_events subsystem with no specific implication in the hardware.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "bf495f91ef5c455af0de679703090566a776b65a", "tree": "17cfc85dd15c87272d0577e517bd9ecfa19aaa79", "parents": [ "8717588413b931818eddc6c9caaa9995c7d2418d" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:45:59 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Oct 01 04:17:14 2024" }, "message": "Add support_hw_smpl description to pfm_get_event_attr_info() man page\n\nWas missing from manual since the field was added.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "8717588413b931818eddc6c9caaa9995c7d2418d", "tree": "c5337e10e4241ef7a65d7f3f5a6d7e5954ceb0e2", "parents": [ "704fb4aa4b722c110256ec0488e8f895542f64ab" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:08:08 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:39:04 2024" }, "message": "Add new attribute info field support_no_mods\n\nThis new attribute is added to the pfm_event_attr_info_t structure\nto handle the case where some of the umasks of an event do not\nsupport all the modifiers that the event as a whole support.\nThat applies to privilege level filtering, hardware sampling and such.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "704fb4aa4b722c110256ec0488e8f895542f64ab", "tree": "d48c4992af9246e4166c5ec0e48a4a16aca021f4", "parents": [ "c89a379175c00a20bbc660ad9b444e8ecc16cd28" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 29 06:07:55 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 30 04:39:04 2024" }, "message": "fix assignment in pfmlib_build_event_pattrs\n\nWas doing os_nattrs +\u003d ..... then os_nattrs was just initialized\nat declaration with no prior usage.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "c89a379175c00a20bbc660ad9b444e8ecc16cd28", "tree": "68d2b120822864c66c791b463a11153631db1105", "parents": [ "6195cbb4686dbeeee7a237ab8a133ef6c2209476" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 04:11:10 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 04:13:28 2024" }, "message": "add ARM Cortex A76 core PMU support\n\nAdds ARM Cortex A76 core PMU support.\nBased on:\n\thttps://github.com/ARM-software/data/blob/master/pmu/cortex-a76.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "6195cbb4686dbeeee7a237ab8a133ef6c2209476", "tree": "2cd8d3b342b4e8585903639fec119472df1e07be", "parents": [ "1e8734203f74f0ec6974a860c0b18cb95cce1371" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 03:50:17 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 03:50:17 2024" }, "message": "fix detection of ARM Cortex A55\n\nWas using code not yet released.\nBug introduced by:\nc40b6eb0640a (\"add ARM Cortex A55 core PMU support\")\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "1e8734203f74f0ec6974a860c0b18cb95cce1371", "tree": "0751d24da7f1170fdc22ddd21d041b57f624a91a", "parents": [ "c40b6eb0640a649b2c3fdf472c1d6499a8e819c0" ], "author": { "name": "Sachin Monga", "email": "smonga@linux.ibm.com", "time": "Thu Aug 15 16:54:51 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 02:56:29 2024" }, "message": "Update IBM Power10 core PMU support\n\nAdded additional events for IBM Power 10 core PMU.\n\nSigned-off-by: Sachin Monga \u003csmonga@linux.ibm.com\u003e\n" }, { "commit": "c40b6eb0640a649b2c3fdf472c1d6499a8e819c0", "tree": "1f54eb10389909d40a481c4cb273386ce494d4a5", "parents": [ "f91ea4f1a76fdd5886fd9b6fe8eaa6f585a5bac4" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 02:47:08 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sun Sep 22 02:50:16 2024" }, "message": "add ARM Cortex A55 core PMU support\n\nAdd support for ARM Cortex A55 core PMU events.\nBased on:\n\thttps://github.com/ARM-software/data/blob/master/pmu/cortex-a55.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "f91ea4f1a76fdd5886fd9b6fe8eaa6f585a5bac4", "tree": "667a7c0bf65436ec3e56315ede403956985b2b19", "parents": [ "892c5fc89ed5fc0e4f0b4a4a290fac57613f23da" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 20 04:23:59 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 20 06:27:17 2024" }, "message": "fix ARM thunderX2 and HiSilicon support to compile on non Linux\n\nThe perf_events encoding routines were mixed with generic encodings\nand event tables. This patch cleans all of this to separate generic\nfrom Linux specific code.\n" }, { "commit": "892c5fc89ed5fc0e4f0b4a4a290fac57613f23da", "tree": "29aa6b5783e29b7a19b0d3c29743c620ef4b615f", "parents": [ "b30681f629517a3159d79dcef0b703687524ad59" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Sep 19 07:38:14 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 20 06:27:17 2024" }, "message": "Add ARM Neoverse V3 core PMU support\n\nBased on:\n https://github.com/ARM-software/data/blob/master/pmu/neoverse-v3.json\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "b30681f629517a3159d79dcef0b703687524ad59", "tree": "dffad1f4487936d9e318160393b513b9d2e82e88", "parents": [ "0118612a28d270e78d1f17c24e9db0935e332285", "25489eac983a6f583a3d7b44f7b1d6a153e90610" ], "author": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Fri Sep 20 06:26:54 2024" }, "committer": { "name": "b\u0027seranian", "email": "allura@localhost", "time": "Fri Sep 20 06:26:54 2024" }, "message": "Merge /u/yselkowitz/perfmon2/ branch gcc14 into master\n\nhttps://sourceforge.net/p/perfmon2/libpfm4/merge-requests/25/\n" }, { "commit": "0118612a28d270e78d1f17c24e9db0935e332285", "tree": "dffad1f4487936d9e318160393b513b9d2e82e88", "parents": [ "3724e7ef87e71dd1de46ef4eb4ec2b1be4ea63e5" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Sep 17 23:36:24 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Sep 18 05:05:01 2024" }, "message": "remove extraneous printf in pfmlib_init_env()\n\nWas introduced by mistake by commit:\n32b7c3d6ab6b (\"add LIBPFM_PROC_CPUINFO variable for Linux\")\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "3724e7ef87e71dd1de46ef4eb4ec2b1be4ea63e5", "tree": "1e4478016a7535f0025575fc80f59e8a5416f5cf", "parents": [ "9c5c88e734e866f0801b80c527330ad6dbe21e89" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 16 05:29:37 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Sep 17 05:33:57 2024" }, "message": "add LIBPFM_PROC_CPUINFO variable for Linux\n\nAllows overriding the filename used to parse the /proc/cpuinfo\nfile. This can be used to detect certain CPU models, such\nas on ARM. Providing an override allows testing without the actual\nhardware.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "9c5c88e734e866f0801b80c527330ad6dbe21e89", "tree": "22d5a38428bc29229d3a52479e0df3088aba3447", "parents": [ "6d276b48eba5ead4e3fd4b6eca359504f2b69b6c" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Sep 11 06:58:35 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Sep 11 07:01:40 2024" }, "message": "add ARM Cortex A72 Core PMU support\n\nAs a clone of Cortex A57.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "6d276b48eba5ead4e3fd4b6eca359504f2b69b6c", "tree": "ee06a7c9b4b1531a7d2dfcf9f3c02d0acc0198d6", "parents": [ "fd3191c34ad87e22d3f3d31d2cf5c1050a9136ba" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Sep 09 16:22:50 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Sep 09 16:25:22 2024" }, "message": "fix pfm_arm_detect() buffer initialization problem\n\nCommit 3abda5bc6c1a (\"Optimize pfm_detect() for ARM processors\")\nadded an optimization to avoid parsing /proc/cpuinfo too many times.\nBut it had a bug whereby it was reinitializing the pfm_arm_cfg.*\nfields multiple times and potentially from an uninitialized buffer.\n\nSigned-off-by: Ian Rogers \u003cirogers@google.com\u003e\n" }, { "commit": "fd3191c34ad87e22d3f3d31d2cf5c1050a9136ba", "tree": "55c23ddb04b28daf5e94e89e6bc7b22e1c22beaa", "parents": [ "0d799b5546477a46b3a52310bbf1884d56e9e37f" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 06 06:38:53 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Sep 06 06:42:33 2024" }, "message": "Fix FRONTEND_RETIRED.LATE_SWPF encoding on Intel GNR\n\nFix was missing from commit d799b554647 (\"update Intel GraniteRapids core PMU to 1.03\")\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "0d799b5546477a46b3a52310bbf1884d56e9e37f", "tree": "267a1ca9b2edd6ecbfe174c4cd4bb22a10dc1da5", "parents": [ "3abda5bc6c1af7f1b620dc594a806b3b5a4134cb" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Sep 03 04:51:03 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Sep 03 04:53:30 2024" }, "message": "update Intel GraniteRapids core PMU to 1.03\n\n Updates the Intel GraniteRapids core PMU event table\n to latest Intel released version:\n\n Date : 08/19/2024\n Version: 1.03\n\n From gitub.com/Intel/perfmon\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n\nupdate Intel GraniteRapids core PMU event table\n\nUpdate to upstream version 1.03\n" }, { "commit": "3abda5bc6c1af7f1b620dc594a806b3b5a4134cb", "tree": "e7992d6ee25b9ff0c5f5da15802e642301f82522", "parents": [ "b8b7d69e774c38618aa440f49d69814d109629f5" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Aug 27 20:52:59 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Aug 27 20:55:41 2024" }, "message": "Optimize pfm_detect() for ARM processors\n\nAvoid calling pfmlib_getcpuinfo_attr() 3 times for each ARM PMU to\ndetect. For a given processor, the function will always return the\nsame information. Use the pfm_arm_cfg structure as a cache on\nsubsequent calls.\n\nNote: this overall logic does not handle ARM hybrids right now.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "b8b7d69e774c38618aa440f49d69814d109629f5", "tree": "eed3d1e35fc24512b6ff21b5a7609bbcd11da049", "parents": [ "0d216ee4082aef2d8cabfa9816cdb6d6560d1d3f" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Aug 27 00:22:47 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Aug 27 00:25:29 2024" }, "message": "add L2D_CACHE and make L2D_CACHE_ACCESS alias for ARM Neoverse N1,N2,V2\n\nTo match kernel and documentation. Patch provides an alias to avoid\nbreaking existing scripts.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "0d216ee4082aef2d8cabfa9816cdb6d6560d1d3f", "tree": "793bb7ee6a0101e954f71dba0ef68367c85253c1", "parents": [ "874ed7cff57271c5d4e530650eadce76e3dcaa14" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Aug 16 07:29:33 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Aug 16 07:29:33 2024" }, "message": "update Intel SapphireRapids core PMU to 1.24\n\nUpdates the Intel SapphireRapids core PMU event table\nto latest Intel released version:\n\nDate : 07/18/2024\nVersion: 1.24\"\n\nFrom gitub.com/Intel/perfmon\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "874ed7cff57271c5d4e530650eadce76e3dcaa14", "tree": "24057fce985da348fdfab65ecc1fb275c6cdff6a", "parents": [ "ffbfc5970897de87471e7cba64737dc13e2369cf" ], "author": { "name": "jdeokkim", "email": "jdeokkim@protonmail.com", "time": "Mon Jul 22 08:08:07 2024" }, "committer": { "name": "jdeokkim", "email": "jdeokkim@protonmail.com", "time": "Mon Jul 22 08:08:07 2024" }, "message": "Fix typos in docs/man3/pfm_get_perf_event_encoding.3\n" }, { "commit": "ffbfc5970897de87471e7cba64737dc13e2369cf", "tree": "038a6bc6b1c6f726e00416ddcaded6927dbf2001", "parents": [ "18f2a3e0541cc438094bbf65ebbed2b6742bf0d4" ], "author": { "name": "jdeokkim", "email": "jdeokkim@protonmail.com", "time": "Mon Jul 22 07:59:06 2024" }, "committer": { "name": "jdeokkim", "email": "jdeokkim@protonmail.com", "time": "Mon Jul 22 07:59:06 2024" }, "message": "Fix typos in docs/man3/pfm_get_os_event_encoding.3\n" }, { "commit": "18f2a3e0541cc438094bbf65ebbed2b6742bf0d4", "tree": "b2dddb53b90499aab68a7c4d45bd4d18fec09748", "parents": [ "e50b6a47c9f9f1386805bbce3d2a634782f8c30e" ], "author": { "name": "Swarup Sahoo", "email": "swarup-chandra.sahoo@amd.com", "time": "Thu Jul 04 20:15:52 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jul 04 20:15:52 2024" }, "message": "Add AMD Zen5 L3 PMU support\n\nThis patch implements support for AMD Zen5 processor L3 cache PMU.\nThe implementation is based on \"Performance Monitor Counters for AMD Family A0h Model 00h- 0Fh Processors, rev 0.02\",\navailable at - https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/58550-0.01.pdf\n\nSigned-off-by: Swarup Sahoo \u003cswarup-chandra.sahoo@amd.com\u003e\n" }, { "commit": "e50b6a47c9f9f1386805bbce3d2a634782f8c30e", "tree": "8318bdf1188ec42147346a93c2210981f698c871", "parents": [ "92c52017d7395c4040ec22949ee8c7f17bc5b4f7" ], "author": { "name": "Swarup Sahoo", "email": "swarup-chandra.sahoo@amd.com", "time": "Thu Jul 04 06:50:15 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jul 04 06:57:18 2024" }, "message": "Add AMD Zen5 core PMU support\n\nThis patch implements support for AMD Zen5 core PMU support.\n\nThe implementation is based on \"Performance Monitor Counters for AMD Family A0h Model 00h- 0Fh Processors, rev 0.02\",\navailable at - https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/58550-0.01.pdf\n\nSigned-off-by: Swarup Sahoo \u003cswarup-chandra.sahoo@amd.com\u003e\n" }, { "commit": "92c52017d7395c4040ec22949ee8c7f17bc5b4f7", "tree": "ccfaa6a8d64544b43924a54e1e84970fbb19438f", "parents": [ "44a55dd97c929087b4ca93540f6bbb2d2efffd15" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 16:17:23 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 16:17:23 2024" }, "message": "add missing pfmlib_intel_gnr.c file\n\nTo complete the Intel GraniteRapids support.\nWas missing from commit 23d0b7c47c2e (\"add Intel GraniteRapids core PMU support\")\nSorry about that.\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "44a55dd97c929087b4ca93540f6bbb2d2efffd15", "tree": "3a04339579ab53c081952279509e853e06e1d57f", "parents": [ "23d0b7c47c2ec06334b3eb378bfc3568b08e0042" ], "author": { "name": "Thomas Richter", "email": "tmricht@linux.ibm.com", "time": "Tue Jun 18 08:17:27 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 05:43:46 2024" }, "message": "s390: Fix calloc compiler error for gcc14\n\nThe definition of calloc is as follows:\n void *calloc(size_t nmemb, size_t size);\nnumber of members is in the first parameter and the\nsize is in the second parameter.\n\nFix error message on the gcc 14 20240102:\n error: \u0027calloc\u0027 sizes specified with \u0027sizeof\u0027 in the earlier\n argument and not in the later argument ...\nby adhering to the calloc() calling convention.\n\nOutput before:\n # make\n Entering directory \u0027/root/perfmon2-libpfm4/lib\u0027\n cc -g -Wall -Werror -Wextra -Wno-unused-parameter -I. \\\n\t -I/root/perfmon2-libpfm4/lib/../include -DCONFIG_PFMLIB_DEBUG \\\n\t -DCONFIG_PFMLIB_OS_LINUX -DCONFIG_PFMLIB_NOTRACEPOINT \\\n\t -DHAS_OPENAT -D_REENTRANT -I. -fvisibility\u003dhidden \\\n\t -DCONFIG_PFMLIB_ARCH_S390X -I. -c pfmlib_s390x_cpumf.c\n pfmlib_s390x_cpumf.c: In function ‘pfm_cpumcf_init’:\n pfmlib_s390x_cpumf.c:221:26: error: ‘calloc’ sizes specified with \\\n\t ‘sizeof’ in the earlier argument and not in the later argument \\\n\t [-Werror\u003dcalloc-transposed-args]\n 221 | cpumcf_pe \u003d calloc(sizeof(*cpumcf_pe), cfvn_set_count):\n | ^\n pfmlib_s390x_cpumf.c:221:26: note: earlier argument should specify\n\tnumber of elements, later size of each element\n\nSigned-off-by: Thomas Richter \u003ctmricht@linux.ibm.com\u003e\nAcked-by: Sumanth Korikkar \u003csumanthk@linux.ibm.com\u003e\n" }, { "commit": "23d0b7c47c2ec06334b3eb378bfc3568b08e0042", "tree": "4d2324eac7f8850ed98cf9762d6324cd6fdeb7e2", "parents": [ "489a940be48980956b27dda89de1eb91b01f185d" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jun 04 06:10:45 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 04:52:58 2024" }, "message": "add Intel GraniteRapids core PMU support\n\nBased on JSON event files published on github.com/Intel/perfmon\nversion 1.02, dated 05/10/2024\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "489a940be48980956b27dda89de1eb91b01f185d", "tree": "27bd6dca7587ffce0fc4571a39318ec99e0127fe", "parents": [ "ace21560113100f4ab5032e99753459ed9da7049" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 04:24:34 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 22 04:26:40 2024" }, "message": "fix Intel SPR inst_retired umask flags\n\nWere missing PEBS and fixed event code umask (ANY) was not encoded\nproperly.\n\ninst_retired.any -\u003e fixed counter 0 encoding 0x100\ninst_retired.any_p -\u003e generic counter encoding 0x00c0\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "ace21560113100f4ab5032e99753459ed9da7049", "tree": "f2edc80184534b150b97f8e1a133a8e96afe4c80", "parents": [ "4bdeb7e067363013257460bdb6c3dbae778b5634" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jun 20 06:32:25 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jun 20 06:34:33 2024" }, "message": "fix validate_x86.c Intel SPR/EMR inst_retired tests\n\nThey were not using the proper event codes for the different\nversions of inst_retired.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "4bdeb7e067363013257460bdb6c3dbae778b5634", "tree": "3314c153e6946d23f5eb564bdd820dfcba5b20ae", "parents": [ "7c486cf96f9eab7019023d40f9c568486f696c44" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 15 05:14:05 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jun 15 05:17:35 2024" }, "message": "Fix encoding of inst_retired.* on Alderlake E-core\n\nWas returning event code 0x0 for both .any and .any_p umasks.\nany_p refers to the generic counter encoding which uses event\ncode 0xc0.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "7c486cf96f9eab7019023d40f9c568486f696c44", "tree": "29455cd561664ddd84231242fde7af691fa2d917", "parents": [ "1c0cdb91bc79eb1bc827e022f0a3738f124796a2" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Apr 25 01:01:23 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Apr 25 01:01:23 2024" }, "message": "remove Intel IcelakeX UNC_CHA_PIPE_REJECT event\n\nEncodings of umasks is invalid and fails to pass tests with perf as it\nsets bits the kernel does not know about.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "1c0cdb91bc79eb1bc827e022f0a3738f124796a2", "tree": "5e0399fc57ec939b3870273971e07fbe7f620c64", "parents": [ "72866cbc2666820d87ebc0af3b1a16d1d5db6965" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Apr 16 00:27:33 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Apr 16 00:27:33 2024" }, "message": "fix uninitialized variable in perf_examples/task.c\n\nCommit 9410619f922f (\"update task.c example to handle hybrid\")\n\nIntroduced a bug by not initializing group_fd which could generate\na compiler warning and a bug.\nFix this by initializing group_fd to -1.\n\nReported-by: William Cohen \u003cwcohen@redhat.com\u003e\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "72866cbc2666820d87ebc0af3b1a16d1d5db6965", "tree": "587a99db31c851b1cf7c9336b348c535bbb6a8d4", "parents": [ "33513ef78f0d81edb277e0d0fd16411abb161297" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Apr 11 15:36:50 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Apr 11 15:36:50 2024" }, "message": "fix duplicate event code for Intel SPR TOPDOWN.BAD_SPEC_SLOTS\n\nWas using same encoding as TOPDOWN.SLOTS.\nFix by adding the proper event code (0xa4) and code override\nflag.\n\nReported-by: \u003claksono@gmail.com\u003e\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "33513ef78f0d81edb277e0d0fd16411abb161297", "tree": "fa5b1e42f082a16897f82691745312d964e1d5e7", "parents": [ "e943f891e9f1d63c4b55bac051ca7b2b3979b25f" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Jan 19 05:55:46 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 01 07:23:31 2024" }, "message": "Add Intel SapphireRapids uncore PMU support for CHA\n\nAdds the Coherence and Home Agent (CHA) for Intel SapphireRapids.\nBased on Intel JSON events v1.17 published from\ngithub.com/intel/perfmon/SPR\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "e943f891e9f1d63c4b55bac051ca7b2b3979b25f", "tree": "68bc65244fc94d23739c1305efb2c2b8d1f15dbc", "parents": [ "10b8044a90ba512be2b10e9425330e989cc22d01" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Jan 16 01:10:28 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 01 07:23:31 2024" }, "message": "Add Intel SapphireRapids uncore PMU support for UPI\n\nAdds the Ultra Path Interconnect PMU (UPI) for Intel SapphireRapids.\nBased on Intel JSON events v1.17 published from\ngithub.com/intel/perfmon/SPR\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "10b8044a90ba512be2b10e9425330e989cc22d01", "tree": "150892fa2e7968f3137b46dc3a9c6d96e7675ea1", "parents": [ "f517f1ec8038de00ce8f5fefeeef704e24aa08ae" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Jan 13 05:55:04 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 01 07:23:31 2024" }, "message": "Add Intel SapphireRapids uncore PMU support for IMC\n\nAdds the memory controller PMU (IMC) for SapphireRapids.\nBased on Intel JSON events v1.17 published from\ngithub.com/intel/perfmon/SPR\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "f517f1ec8038de00ce8f5fefeeef704e24aa08ae", "tree": "7f7c718ca5415b085b49695d75e216687c17ee25", "parents": [ "816bb547f8997b84f7ef70bb99420f40dc8a984d" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 01 07:07:21 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Mar 01 07:10:56 2024" }, "message": "add CONFIG_PFMLIB_NOTRACEPOINT to speedup libpfm4 initialization\n\nWhen pfmlib_initialize() is run as root and if the debugs is mounted,\nthen the library parses all the tracepoints to add them to the perf PMU.\nDepending on the number of tracepoints, this can take a significant amount\nof time even though this may not be needed if no tracepoints is passed.\nIn order to speedup pfm_initialize(), the patch adds a compile-time option\nto disable support for tracepoint in the perf PMU.\n\nTo deactivate tracepoint support: make CONFIG_PFMLIB_NOTRACEPOINT\u003dy\n\nThe default build is unchanged with tracepoints enabled. This patch\nadds an opt-out option.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "816bb547f8997b84f7ef70bb99420f40dc8a984d", "tree": "06cf70da9cbe3b2fae4968bdd691a044e4045deb", "parents": [ "8fa4467ffa7014ed8f1525783b5919b80117beca" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Feb 27 06:39:49 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:42:26 2024" }, "message": "add Intel Raptorlake PMU support\n\nEnables support for Raptorlake, Raptorlake P, Raptorlake S.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "8fa4467ffa7014ed8f1525783b5919b80117beca", "tree": "b38328fe7d40eb692f3c46efda8efd7945e15005", "parents": [ "e84a9563f4c93dc6e530dfa55d61b150fbf51510" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Feb 20 06:58:17 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:41:54 2024" }, "message": "Add Intel AlderLake Gracemont (E-Core) core PMU support\n\nAdds core PMU support for Alderlake E-core (gracemont).\nBased on Intel JSON events v1.24 published from\ngithub.com/intel/perfmon/ADL\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "e84a9563f4c93dc6e530dfa55d61b150fbf51510", "tree": "31ba153cb7c0819fbee7a08b7d1bee3191798059", "parents": [ "9410619f922facca7dab2406c58fe41a8dd61529" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 15 07:09:49 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:41:22 2024" }, "message": "Add Intel AlderLake Goldencove (P-Core) core PMU support\n\nAdds core PMU support for Alderlake P-core (goldencove).\nBased on Intel JSON events v1.24 published from\ngithub.com/intel/perfmon/ADL\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "9410619f922facca7dab2406c58fe41a8dd61529", "tree": "2e9e391488ef0efbe4a2094de3cf65e3e99e4353", "parents": [ "2441b263f6f28c0fe80f8cee62cd2e64d75cd433" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Feb 21 07:22:47 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:10:14 2024" }, "message": "update task.c example to handle hybrid\n\nCannot group event if they do not belong to the same hardware PMU.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "2441b263f6f28c0fe80f8cee62cd2e64d75cd433", "tree": "ef537f6ae6071e2d8e47e9327b0051e1353e13a7", "parents": [ "9669e0d696a98b8b5655186dda8b457113cb0ba2" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:08:30 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Feb 29 04:10:14 2024" }, "message": "add INTEL_X86_CODE_DUP event flag for Intel PMUs\n\nTo handle the case where two events shared the same code and none\nis because of deprecation. In order to pass validation both events\nwith the same code must have that flag set.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "9669e0d696a98b8b5655186dda8b457113cb0ba2", "tree": "a652f4b450fc0d9f47522be828915c593cebccce", "parents": [ "b7307408ddb1548271983d1fd7c4f17287d2dc0e" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Feb 20 06:48:44 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Feb 21 05:53:58 2024" }, "message": "Add support for deprecated events for Intel X86 PMUs\n\nAdds INTEL_X86_DEPRECATED flag to Intel X86 events.\nDeprecated in this context means there is a newer event\nmonitoring the same condition. This is used to mark events\nas deprecated and avoid detecting duplicate event codes.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "b7307408ddb1548271983d1fd7c4f17287d2dc0e", "tree": "f5a8a110dcf1fb3ecc91f561625ffe920f39ca6a", "parents": [ "0d4ed0e7b09338e1bb1ab9153beab030c52570fe" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Feb 14 05:58:11 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Feb 14 05:59:24 2024" }, "message": "fix Intel IcelakeX uncore PCU PMU man page typo\n\nWas referring to eRP clockticks instead of PCU clockticks.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "0d4ed0e7b09338e1bb1ab9153beab030c52570fe", "tree": "91698c5392060d7da6f5e54bfa035028bc7a9d2c", "parents": [ "ce35cb6615ff7973cd0e847e0989d2a8306e3312" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Feb 03 00:26:28 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Feb 03 00:33:04 2024" }, "message": "fix missing PEBS flag on Intel SPR MEM_LOAD_L3_MISS_RETIRED\n\ncommit 769b239ee314 (\"add PEBS support to Intel SPR MEM_LOAD_L3_MISS_RETIRED\")\nadded the PEBS flag to the event but to none of the umasks causing a validation\nissue. Add missing PEBS flags to the umasks\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "ce35cb6615ff7973cd0e847e0989d2a8306e3312", "tree": "dfe9d1f8fded83752bd52751e1a36014df860b98", "parents": [ "769b239ee31465f030f63d8dd16c6be006bfcb55" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jan 11 06:08:52 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Feb 02 23:42:48 2024" }, "message": "add Intel IcelakeX IMC PMU validation tests\n\nWas missing from original patch.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "769b239ee31465f030f63d8dd16c6be006bfcb55", "tree": "eab5aaddc6603a65818c45ea02ab09b1f74e4d7f", "parents": [ "7dbcf34a869ee74909142d9065f0b5b56119752e" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Feb 02 23:32:27 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Fri Feb 02 23:39:56 2024" }, "message": "add PEBS support to Intel SPR MEM_LOAD_L3_MISS_RETIRED\n\nWas missing PEBS flag.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "25489eac983a6f583a3d7b44f7b1d6a153e90610", "tree": "6b55f858bf9a40433e82ce614a041afde6f92bcc", "parents": [ "90f61a008cdee50d085b5041414df55e16e045fe" ], "author": { "name": "Yaakov Selkowitz", "email": "yselkowi@redhat.com", "time": "Tue Jan 23 20:41:15 2024" }, "committer": { "name": "Yaakov Selkowitz", "email": "yselkowi@redhat.com", "time": "Tue Jan 23 20:41:15 2024" }, "message": "Fix for GCC 14\n\npfmlib_s390x_cpumf.c: In function ‘pfm_cpumcf_init’:\npfmlib_s390x_cpumf.c:219:34: error: ‘calloc’ sizes specified with ‘sizeof’ in the earlier argument and not in the later argument [-Werror\u003dcalloc-transposed-args]\n 219 | cpumcf_pe \u003d calloc(sizeof(*cpumcf_pe),\n | ^\npfmlib_s390x_cpumf.c:219:34: note: earlier argument should specify number of elements, later size of each element\n\nSigned-off-by: Yaakov Selkowitz \u003cyselkowi@redhat.com\u003e\n" }, { "commit": "7dbcf34a869ee74909142d9065f0b5b56119752e", "tree": "1ce20461c775169204f7da4c6725fa272a2a03a3", "parents": [ "90f61a008cdee50d085b5041414df55e16e045fe" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Jan 03 20:21:16 2024" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Jan 11 06:03:14 2024" }, "message": "fix number of counter on Intel IcelakeX IRP uncore PMU\n\nIntel IcelakeX IRP has only two counters.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "90f61a008cdee50d085b5041414df55e16e045fe", "tree": "10a633633082b8e22b7ba408af1be35f8be19ce3", "parents": [ "22afed4c1020b579205ac8e8f9d6e8599307b9ee" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 18 09:00:31 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:27 2023" }, "message": "Add Intel IcelakeX uncore PMU support for M2PCIE\n\nAdds the Mesh to IIO PMU (M2PCIE) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "22afed4c1020b579205ac8e8f9d6e8599307b9ee", "tree": "ad776f15e76fad587abc0bad5d48518fb82ceb3e", "parents": [ "cdbe2eed7bdcf5d45086d6730033defc1939a722" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 18 05:25:51 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:27 2023" }, "message": "Add Intel IcelakeX uncore PMU support for UBOX\n\nAdds the UBOX PMU (UBOX) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "cdbe2eed7bdcf5d45086d6730033defc1939a722", "tree": "b1345d52d1c3890e96ecef38bf63a1ba9d2f0e97", "parents": [ "17dddc2f4cde87f37f041f40586654190da5a8c2" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Dec 13 07:27:19 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:26 2023" }, "message": "Add Intel IcelakeX uncore PMU support for M3UPI\n\nAdds the Mesh to UPI PMU (M3UPI) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "17dddc2f4cde87f37f041f40586654190da5a8c2", "tree": "2e6eed1ee1827fb2798827e4de08f3afac26fec3", "parents": [ "32fcf6fe2eaf2f2bf105f7543dcc0b07c097baaf" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Dec 13 06:13:47 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:26 2023" }, "message": "Add Intel IcelakeX uncore PMU support for UPI\n\nAdds the Ultra Path Interconnect PMU support (UPI) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "32fcf6fe2eaf2f2bf105f7543dcc0b07c097baaf", "tree": "2dc8ba6e3bfc1b4b28aed340ed57f5f1e49bf3f8", "parents": [ "20ff7523ffaae04f6762d51e32fe35e04fa70cad" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 11 06:45:04 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:26 2023" }, "message": "Add Intel IcelakeX uncore PMU support for PCU\n\nAdds the Power Control unit PMU support (PCU) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "20ff7523ffaae04f6762d51e32fe35e04fa70cad", "tree": "3dc010dd860b0a9a7f1df7bc80787b4fed34cf39", "parents": [ "d5ed0e03686c051f5311fc1993824245eb10e1d2" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 09 07:24:44 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:26 2023" }, "message": "Add Intel IcelakeX uncore PMU support for M2M\n\nAdds the Mesh to Memory PMU support (M2M) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "d5ed0e03686c051f5311fc1993824245eb10e1d2", "tree": "e944a375ee45ae6161df528174d9a2aee2ae6b38", "parents": [ "30afdce909bcc7313af7599cfbf6484ae4b1fc3e" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Dec 06 05:17:16 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Sat Dec 30 00:45:25 2023" }, "message": "Add Intel IcelakeX uncore PMU support for IRP\n\nAdds the PCIe IIO Ring Port PMU support (IRP) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "30afdce909bcc7313af7599cfbf6484ae4b1fc3e", "tree": "9078fa66f01c1d5d91b3faa2aa3a6c6f3fe8c0ef", "parents": [ "6237022aa77bc9c845b1c48d741e54bdc22ac077" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Dec 05 06:08:00 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 18 08:13:25 2023" }, "message": "Add Intel IcelakeX uncore PMU support for IIO\n\nAdds the PCIe I/O controller PMU support (IIO) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\n github.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "6237022aa77bc9c845b1c48d741e54bdc22ac077", "tree": "d85bc90652b7935ac521ae0a187bf8f99bb5c759", "parents": [ "05f04adec932cd2cd28e83f718e4e0ae6ba2eab4" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Thu Nov 23 00:37:53 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 18 07:59:42 2023" }, "message": "Add Intel IcelakeX uncore PMU support for IMC\n\nAdds the memory controller PMU support (IMC) for Intel IcelakeX.\nBased on Intel JSON events v1.21 published from\ngithub.com/intel/perfmon/ICX\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "05f04adec932cd2cd28e83f718e4e0ae6ba2eab4", "tree": "15616c4b35e0a75ed356d7429dd19041165cc037", "parents": [ "94e82e27c02ef01f288a1b40904d72b2954d3f31" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Wed Nov 22 23:46:42 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 18 07:49:17 2023" }, "message": "Add Intel IcelakeX uncore PMU support for CHA\n\nAdds Intel IcelakeX CHA (Coherency and Home Agent) uncore PMU support.\nBased on Intel published uncore JSON events v1.21 from\ngithub.com/intel/perfmon/ICX.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" }, { "commit": "94e82e27c02ef01f288a1b40904d72b2954d3f31", "tree": "a74726bc48d6cd86209ac9cb10c353fb12f5b5ee", "parents": [ "d058479bd048d2742df298097da86bc86dd1a5ce" ], "author": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Mon Dec 11 06:28:11 2023" }, "committer": { "name": "Stephane Eranian", "email": "eranian@gmail.com", "time": "Tue Dec 12 20:14:59 2023" }, "message": "check umasks[] bounds in intel_x86_uflag()\n\nOtherwise may run into SEGFAULT for some events.\n\nSigned-off-by: Stephane Eranian \u003ceranian@gmail.com\u003e\n" } ], "next": "d058479bd048d2742df298097da86bc86dd1a5ce" }