diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
index 0eeeb7e..5a0b457 100644
--- a/lib/events/s390x_cpumf_events.h
+++ b/lib/events/s390x_cpumf_events.h
@@ -2843,6 +2843,641 @@
 	},
 };
 
+static const pme_cpumf_ctr_t cpumcf_z17_counters[] = {
+	{
+		.ctrnum = 128,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "L1D_RO_EXCL_WRITES",
+		.desc = "A directory write to the Level-1 Data cache where"
+			" the line was originally in a Read-Only state in the"
+			" cache but has been updated to be in the Exclusive"
+			" state that allows stores to the cache line.",
+	},
+	{
+		.ctrnum = 129,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DTLB2_WRITES",
+		.desc = "A translation has been written into The Translation"
+			" Lookaside Buffer 2 (TLB2) and the request was made"
+			" by the Level-1 Data cache. This is a replacement"
+			" for what was provided for the DTLB on z13 and prior"
+			" machines.",
+	},
+	{
+		.ctrnum = 130,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DTLB2_MISSES",
+		.desc = "A TLB2 miss is in progress for a request made by"
+			" the Level-1 Data cache. Incremented by one for"
+			" every TLB2 miss in progress for the Level-1 Data"
+			" cache on this cycle. This is a replacement for what"
+			" was provided for the DTLB on z13 and prior"
+			" machines.",
+	},
+	{
+		.ctrnum = 131,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "CRSTE_1MB_WRITES",
+		.desc = "A translation entry was written into the Combined"
+			" Region and Segment Table Entry array in the Level-2"
+			" TLB for a one-megabyte page.",
+	},
+	{
+		.ctrnum = 132,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DTLB2_GPAGE_WRITES",
+		.desc = "A translation entry for a two-gigabyte page was"
+			" written into the Level-2 TLB.",
+	},
+	{
+		.ctrnum = 134,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ITLB2_WRITES",
+		.desc = "A translation entry has been written into the"
+			" Translation Lookaside Buffer 2 (TLB2) and the"
+			" request was made by the Level-1 Instruction cache."
+			" This is a replacement for what was provided for the"
+			" ITLB on z13 and prior machines.",
+	},
+	{
+		.ctrnum = 135,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ITLB2_MISSES",
+		.desc = "A TLB2 miss is in progress for a request made by"
+			" the Level-1 Instruction cache. Incremented by one"
+			" for every TLB2 miss in progress for the Level-1"
+			" Instruction cache in a cycle. This is a replacement"
+			" for what was provided for the ITLB on z13 and prior"
+			" machines.",
+	},
+	{
+		.ctrnum = 137,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TLB2_PTE_WRITES",
+		.desc = "A translation entry was written into the Page Table"
+			" Entry array in the Level-2 TLB.",
+	},
+	{
+		.ctrnum = 138,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TLB2_CRSTE_WRITES",
+		.desc = "Translation entries were written into the Combined"
+			" Region and Segment Table Entry array and the Page"
+			" Table Entry array in the Level-2 TLB.",
+	},
+	{
+		.ctrnum = 139,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TLB2_ENGINES_BUSY",
+		.desc = "The number of Level-2 TLB translation engines busy"
+			" in a cycle.",
+	},
+	{
+		.ctrnum = 140,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TX_C_TEND",
+		.desc = "A TEND instruction has completed in a constrained"
+			" transactional-execution mode.",
+	},
+	{
+		.ctrnum = 141,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TX_NC_TEND",
+		.desc = "A TEND instruction has completed in a non-"
+			" constrained transactional-execution mode.",
+	},
+	{
+		.ctrnum = 143,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "L1C_TLB2_MISSES",
+		.desc = "Increments by one for any cycle where a Level-1"
+			" cache or Level-2 TLB miss is in progress.",
+	},
+	{
+		.ctrnum = 145,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_REQ",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache.",
+	},
+	{
+		.ctrnum = 146,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_REQ_IV",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache with"
+			" intervention.",
+	},
+	{
+		.ctrnum = 147,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_REQ_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache after using"
+			" chip level horizontal persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 148,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_REQ_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache after using"
+			" drawer level horizontal persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 149,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_CHIP",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache.",
+	},
+	{
+		.ctrnum = 150,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_CHIP_IV",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache with intervention.",
+	},
+	{
+		.ctrnum = 151,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_CHIP_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache after using chip"
+			" level horizontal persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 152,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_CHIP_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache after using drawer"
+			" level horizontal persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 153,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_MODULE",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Module Level-2 cache.",
+	},
+	{
+		.ctrnum = 154,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_DRAWER",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Drawer Level-2 cache.",
+	},
+	{
+		.ctrnum = 155,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_OFF_DRAWER",
+		.desc = "A directory write to the Level-1 Data cache"
+			" directory where the returned cache line was sourced"
+			" from an Off-Drawer Level-2 cache.",
+	},
+	{
+		.ctrnum = 156,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_CHIP_MEMORY",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from On-Chip memory.",
+	},
+	{
+		.ctrnum = 157,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_MODULE_MEMORY",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from On-Module memory.",
+	},
+	{
+		.ctrnum = 158,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_ON_DRAWER_MEMORY",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from On-Drawer memory.",
+	},
+	{
+		.ctrnum = 159,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DCW_OFF_DRAWER_MEMORY",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from Off-Drawer memory.",
+	},
+	{
+		.ctrnum = 160,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_MODULE_IV",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from an On-Module Level-2"
+			" cache with intervention.",
+	},
+	{
+		.ctrnum = 161,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_MODULE_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from an On-Module Level-2"
+			" cache after using chip level horizontal"
+			" persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 162,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_MODULE_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from an On-Module Level-2"
+			" cache after using drawer level horizontal"
+			" persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 163,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_DRAWER_IV",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from an On-Drawer Level-2"
+			" cache with intervention.",
+	},
+	{
+		.ctrnum = 164,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_DRAWER_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" instruction cache directory where the returned"
+			" cache line was sourced from an On-Drawer Level-2"
+			" cache after using chip level horizontal"
+			" persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 165,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_ON_DRAWER_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" instruction cache directory where the returned"
+			" cache line was sourced from an On-Drawer Level-2"
+			" cache after using drawer level horizontal"
+			" persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 166,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_OFF_DRAWER_IV",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" instruction cache directory where the returned"
+			" cache line was sourced from an Off-Drawer Level-2"
+			" cache with intervention.",
+	},
+	{
+		.ctrnum = 167,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_OFF_DRAWER_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" instruction cache directory where the returned"
+			" cache line was sourced from an Off-Drawer Level-2"
+			" cache after using chip level horizontal"
+			" persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 168,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "IDCW_OFF_DRAWER_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Data or Level-1"
+			" Instruction cache directory where the returned"
+			" cache line was sourced from an Off-Drawer Level-2"
+			" cache after using drawer level horizontal"
+			" persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 169,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_REQ",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" the requestors Level-2 cache.",
+	},
+	{
+		.ctrnum = 170,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_REQ_IV",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache with"
+			" intervention.",
+	},
+	{
+		.ctrnum = 171,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_REQ_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache after using"
+			" chip level horizontal persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 172,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_REQ_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from the requestors Level-2 cache after using"
+			" drawer level horizontal persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 173,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_CHIP",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache.",
+	},
+	{
+		.ctrnum = 174,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_CHIP_IV",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache with intervention.",
+	},
+	{
+		.ctrnum = 175,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_CHIP_CHIP_HIT",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip Level-2 cache after using chip"
+			" level horizontal persistence, Chip-HP hit.",
+	},
+	{
+		.ctrnum = 176,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_CHIP_DRAWER_HIT",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Chip level 2 cache after using drawer"
+			" level horizontal persistence, Drawer-HP hit.",
+	},
+	{
+		.ctrnum = 177,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_MODULE",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Module Level-2 cache.",
+	},
+	{
+		.ctrnum = 178,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_ON_DRAWER",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an On-Drawer Level-2 cache.",
+	},
+	{
+		.ctrnum = 179,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "ICW_OFF_DRAWER",
+		.desc = "A directory write to the Level-1 Instruction cache"
+			" directory where the returned cache line was sourced"
+			" from an Off-Drawer Level-2 cache.",
+	},
+	{
+		.ctrnum = 202,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "CYCLES_SAMETHRD",
+		.desc = "The number of cycles the CPU is not in wait state"
+			" and the CPU is running by itself on the Core.",
+	},
+	{
+		.ctrnum = 203,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "CYCLES_DIFFTHRD",
+		.desc = "The number of cycles the CPU is not in wait state"
+			" and the CPU is running with another thread on the"
+			" Core.",
+	},
+	{
+		.ctrnum = 204,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "INST_SAMETHRD",
+		.desc = "The number of instructions executed on the CPU and"
+			" the CPU is running by itself on the Core.",
+	},
+	{
+		.ctrnum = 205,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "INST_DIFFTHRD",
+		.desc = "The number of instructions executed on the CPU and"
+			" the CPU is running with another thread on the Core.",
+	},
+	{
+		.ctrnum = 206,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "WRONG_BRANCH_PREDICTION",
+		.desc = "A count of the number of branches that were"
+			" predicted incorrectly by the branch prediction"
+			" logic in the Core. This includes incorrectly"
+			" predicted branches that are executed in Firmware."
+			" Examples of instructions implemented in Firmware"
+			" are complicated instructions like MVCL (Move"
+			" Character Long) and PC (Program Call).",
+	},
+	{
+		.ctrnum = 225,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "VX_BCD_EXECUTION_SLOTS",
+		.desc = "Count of floating point execution slots used for"
+			" finished vector arithmetic Binary Coded Decimal"
+			" instructions. Instructions: VAP, VSP, VMP, VMSP,"
+			" VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ,"
+			" VUPKZ, VCVB, VCVBG, VCVD, VCVDG, VSCHP, VSCSHP,"
+			" VCSPH, VCLZDP, VPKZR, VSRPR, VUPKZH, VUPKZL, VTZ,"
+			" VUPH, VUPL, VCVBX, VCVDX.",
+	},
+	{
+		.ctrnum = 226,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DECIMAL_INSTRUCTIONS",
+		.desc = "Decimal instruction dispatched. Instructions: CVB,"
+			" CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP, TP.",
+	},
+	{
+		.ctrnum = 232,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "LAST_HOST_TRANSLATIONS",
+		.desc = "Last Host Translation done.",
+	},
+	{
+		.ctrnum = 244,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TX_NC_TABORT",
+		.desc = "A transaction abort has occurred in a non-"
+			" constrained transactional-execution mode.",
+	},
+	{
+		.ctrnum = 245,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TX_C_TABORT_NO_SPECIAL",
+		.desc = "A transaction abort has occurred in a constrained"
+			" transactional-execution mode and the CPU is not"
+			" using any special logic to allow the transaction to"
+			" complete.",
+	},
+	{
+		.ctrnum = 246,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "TX_C_TABORT_SPECIAL",
+		.desc = "A transaction abort has occurred in a constrained"
+			" transactional-execution mode and the CPU is using"
+			" special logic to allow the transaction to complete.",
+	},
+	{
+		.ctrnum = 248,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DFLT_ACCESS",
+		.desc = "Cycles CPU spent obtaining access to Deflate unit.",
+	},
+	{
+		.ctrnum = 253,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DFLT_CYCLES",
+		.desc = "Cycles CPU is using Deflate unit.",
+	},
+	{
+		.ctrnum = 256,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "SORTL",
+		.desc = "Increments by one for every SORT LISTS (SORTL)"
+			" instruction executed.",
+	},
+	{
+		.ctrnum = 265,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DFLT_CC",
+		.desc = "Increments by one for every DEFLATE CONVERSION CALL"
+			" (DFLTCC) instruction executed.",
+	},
+	{
+		.ctrnum = 266,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "DFLT_CCFINISH",
+		.desc = "Increments by one for every DEFLATE CONVERSION CALL"
+			" (DFLTCC) instruction executed that ended in"
+			" Condition Codes 0, 1 or 2.",
+	},
+	{
+		.ctrnum = 267,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_INVOCATIONS",
+		.desc = "Increments by one for every NEURAL NETWORK"
+			" PROCESSING ASSIST (NNPA) instruction executed.",
+	},
+	{
+		.ctrnum = 268,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_COMPLETIONS",
+		.desc = "Increments by one for every NEURAL NETWORK"
+			" PROCESSING ASSIST (NNPA) instruction executed that"
+			" ended in Condition Code 0.",
+	},
+	{
+		.ctrnum = 269,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_WAIT_LOCK",
+		.desc = "Cycles CPU spent obtaining access to IBM Z"
+			" Integrated Accelerator for AI.",
+	},
+	{
+		.ctrnum = 270,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_HOLD_LOCK",
+		.desc = "Cycles CPU is using IBM Z Integrated Accelerator"
+			" for AI.",
+	},
+	{
+		.ctrnum = 272,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_INST_ONCHIP",
+		.desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)"
+			" instruction has used the Local On-Chip IBM Z"
+			" Integrated Accelerator for AI during its execution",
+	},
+	{
+		.ctrnum = 273,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_INST_OFFCHIP",
+		.desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)"
+			" instruction has used an Off-Chip IBM Z Integrated"
+			" Accelerator for AI during its execution.",
+	},
+	{
+		.ctrnum = 274,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_INST_DIFF",
+		.desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)"
+			" instruction has used a different IBM Z Integrated"
+			" Accelerator for AI since it was last executed.",
+	},
+	{
+		.ctrnum = 276,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_4K_PREFETCH",
+		.desc = "Number of 4K prefetches done for a remote IBM Z"
+			" Integated Accelerator for AI.",
+	},
+	{
+		.ctrnum = 277,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_COMPL_LOCK",
+		.desc = "A PERFORM LOCKED OPERATION (PLO) has completed.",
+	},
+	{
+		.ctrnum = 278,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_RETRY_LOCK",
+		.desc = "A PERFORM LOCKED OPERATION (PLO) has been retried and"
+			" the CPU did not use any special logic to allow the"
+			" PLO to complete.",
+	},
+	{
+		.ctrnum = 279,
+		.ctrset = CPUMF_CTRSET_EXTENDED,
+		.name = "NNPA_RETRY_LOCK_WITH_PLO",
+		.desc = "A PERFORM LOCKED OPERATION (PLO) has been retried and"
+			" the CPU is using special logic to allow PLO to"
+			" complete.",
+	},
+	{
+		.ctrnum = 448,
+		.ctrset = CPUMF_CTRSET_MT_DIAG,
+		.name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
+		.desc = "Cycle count with one thread active",
+	},
+	{
+		.ctrnum = 449,
+		.ctrset = CPUMF_CTRSET_MT_DIAG,
+		.name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
+		.desc = "Cycle count with two threads active",
+	},
+};
+
 static const pme_cpumf_ctr_t cpumsf_counters[] = {
 	{
 		.ctrnum = 720896,
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
index 718f5f8..35c1853 100644
--- a/lib/pfmlib_s390x_cpumf.c
+++ b/lib/pfmlib_s390x_cpumf.c
@@ -168,7 +168,7 @@
 	/* counters based on second version number */
 	csvn_set = cpumcf_svn_generic_counters;
 	csvn_set_count = LIBPFM_ARRAY_SIZE(cpumcf_svn_generic_counters);
-	if (csvn < 6)	/* Crypto counter set enlarged for SVN == 6 */
+	if (csvn < 6)	/* Crypto counter set enlarged for SVN == 6 7 and 8 */
 		csvn_set_count -= CPUMF_SVN6_ECC;
 
 	/* check and assign a machine-specific extended counter set */
@@ -208,6 +208,11 @@
 		ext_set = cpumcf_z16_counters;
 		ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z16_counters);
 		break;
+	case 9175:  /* IBM Machine types 9175 and 9176 */
+	case 9176:
+		ext_set = cpumcf_z17_counters;
+		ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z17_counters);
+		break;
 	default:
 		/* No extended counter set for this machine type or there
 		 * was an error retrieving the machine type */