CHROMIUM: ARM: tegra: aebl: Update EMC tables to match kernel.
This depends on:
* http://gerrit.chromium.org/gerrit/5206
Tegra: pmu: Fix the pmu_read and pmu_write
* http://gerrit.chromium.org/gerrit/5238
CHROMIUM: ARM: tegra: Don't call board_emc_init() before
bi_arch_number set.
This should have been done at the same time as these kernel CLs:
* http://gerrit.chromium.org/gerrit/4516
CHROMIUM: arm: tegra: Modify DVFS EMC table to support all sku of Aebl-DVT
BUG=chromium-os:18648
TEST=Added print statements and saw proper init.
TEST=Booted on aebl and saw things were OK.
Reviewed-on: http://gerrit.chromium.org/gerrit/5254
Tested-by: Doug Anderson <[email protected]>
Reviewed-by: Hung-Te Lin <[email protected]>
(cherry picked from commit 098bf3e25be1471a63b5c8824f02990c560ae9fe)
Change-Id: I2d23f27d7108b711760c15b166821ec126224fc1
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
index 07fda2b..3609ef8 100644
--- a/board/nvidia/common/emc.c
+++ b/board/nvidia/common/emc.c
@@ -634,7 +634,7 @@
}
}
-static const struct tegra_emc_table aebl_emc_tables[] = {
+static const struct tegra_emc_table aebl_emc_tables_Micron_380Mhz[] = {
{
.rate = 190000, /* SDRAM frequency */
.regs = {
@@ -652,7 +652,7 @@
0x00000001, /* REXT */
0x00000003, /* WDV */
0x00000004, /* QUSE */
- 0x00000005, /* QRST */
+ 0x00000003, /* QRST */
0x00000009, /* QSAFE */
0x0000000c, /* RDV */
0x0000059f, /* REFRESH */
@@ -676,7 +676,7 @@
0x00000000, /* ODT_READ */
0x00000083, /* FBIO_CFG5 */
0xa06204ae, /* CFG_DIG_DLL */
- 0x007e8010, /* DLL_XFORM_DQS */
+ 0x007e4010, /* DLL_XFORM_DQS */
0x00000000, /* DLL_XFORM_QUSE */
0x00000000, /* ZCAL_REF_CNT */
0x00000000, /* ZCAL_WAIT_CNT */
@@ -738,9 +738,137 @@
}
};
+static const struct tegra_emc_table aebl_emc_tables_Hynix_380Mhz[] = {
+ {
+ .rate = 190000, /* SDRAM frequency */
+ .regs = {
+ 0x0000000c, /* RC */
+ 0x00000026, /* RFC */
+ 0x00000009, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000004, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x0000000c, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000001, /* REXT */
+ 0x00000004, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000009, /* QSAFE */
+ 0x0000000d, /* RDV */
+ 0x0000059f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000003, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000b, /* RW2PDEN */
+ 0x000000c8, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000007, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x0000000f, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000000, /* TREFBW */
+ 0x00000000, /* QUSE_EXTRA */
+ 0x00000003, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000083, /* FBIO_CFG5 */
+ 0xa06204ae, /* CFG_DIG_DLL */
+ 0x007e0010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000000, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ }, {
+ .rate = 380000, /* SDRAM frequency */
+ .regs = {
+ 0x00000017, /* RC */
+ 0x0000004b, /* RFC */
+ 0x00000012, /* RAS */
+ 0x00000006, /* RP */
+ 0x00000004, /* R2W */
+ 0x00000005, /* W2R */
+ 0x00000003, /* R2P */
+ 0x0000000c, /* W2P */
+ 0x00000006, /* RD_RCD */
+ 0x00000006, /* WR_RCD */
+ 0x00000003, /* RRD */
+ 0x00000001, /* REXT */
+ 0x00000004, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000009, /* QSAFE */
+ 0x0000000d, /* RDV */
+ 0x00000b5f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000006, /* PCHG2PDEN */
+ 0x00000006, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x00000011, /* RW2PDEN */
+ 0x000000c8, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x0000000e, /* TFAW */
+ 0x00000007, /* TRPAB */
+ 0x0000000f, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000000, /* TREFBW */
+ 0x00000000, /* QUSE_EXTRA */
+ 0x00000003, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000083, /* FBIO_CFG5 */
+ 0xe044048b, /* CFG_DIG_DLL */
+ 0x007da010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000000, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ }
+};
+
+struct tegra_board_emc_table aebl_emc[] = {
+ {
+ .table = aebl_emc_tables_Micron_380Mhz,
+ .table_size = ARRAY_SIZE(aebl_emc_tables_Micron_380Mhz),
+ .name = "Mircron 380MHz",
+ },
+ {
+ .table = aebl_emc_tables_Hynix_380Mhz,
+ .table_size = ARRAY_SIZE(aebl_emc_tables_Hynix_380Mhz),
+ .name = "Hynix 380MHz",
+ },
+};
+
void aebl_emc_init(void)
{
- tegra_set_emc(aebl_emc_tables, ARRAY_SIZE(aebl_emc_tables));
+ u32 reg;
+ int ram_id;
+
+ reg = readl(NV_PA_APB_MISC_BASE + STRAP_OPT);
+ ram_id = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
+
+ if (ram_id >= ARRAY_SIZE(aebl_emc) || !aebl_emc[ram_id].table) {
+ tegra_set_emc(NULL, 0);
+ } else {
+ tegra_set_emc(aebl_emc[ram_id].table,
+ aebl_emc[ram_id].table_size);
+ }
}
/* These values are not final, but they do work on the board */
