Check ICH erase command support at run time.
When deciding which erasers should be used for a certain flashrom
session, one needs to take into account the fact that Intel SPI
controller (included in the ICH) could be allowing only a subset of
erase commands supported by the flash chip.
Instead of hardcoding the susbsets of supported commands let's
introduce the 'dry run' mode, where the command is invoked and
verified by the ICH driver, but actual action is not taken.
The nonzero return code indicates that a command is not supported by
the controller.
Note that ICH support should be verified only when programming the
main AP flash, ICH is not involved when programming the EC.
BRANCH=none
BUG=b:862703, chromium:860142
TEST=verified that previously failing tests succeed on auron and cyan.
On auron, cyan and eve verified that reprogramming flash spaces
of 4K, 16K, 32K, 64K and 128K bytes works as expected.
Change-Id: Ifa248c9d42c28c644373fb28ec6a3d710211c228
Signed-off-by: Vadim Bendebury <[email protected]>
Reviewed-on: https://chromium-review.googlesource.com/1139405
Reviewed-by: Simon Glass <[email protected]>
(cherry picked from commit 066143d2557019640aad77a3d69f199aabd1d47e)
Reviewed-on: https://chromium-review.googlesource.com/1152186
4 files changed
