Update PSP Bootloader to v0.8.B.7B
PSP BL Release (Version 0.8.B.7B)
================================
Date: 1st Oct 2020
- Introduce OEM app PSP BL info structure
- Remove assert if booted on non-chromebook to boot on Mandolin
- Testcase for PKCS#1 v1.5 based ModExp svc
- Enable MODEXP SVC to OEM APP.
- PSP FW is updated to 0.8.B.7B
BUG=b:168895748 b:168984226 b:169157796
TEST=Build & boot zork boards with signed verstage.
BRANCH=Zork
Change-Id: Ibffd222dbe04a9662fc763321ea7c977ddc92ed6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/amd_blobs/+/2442643
Tested-by: Martin Roth <[email protected]>
Reviewed-by: Kangheui Won <[email protected]>
Commit-Queue: Kangheui Won <[email protected]>
diff --git a/picasso/PSP/PSP_ReleaseNote.txt b/picasso/PSP/PSP_ReleaseNote.txt
index 4d697a0..539af13 100644
--- a/picasso/PSP/PSP_ReleaseNote.txt
+++ b/picasso/PSP/PSP_ReleaseNote.txt
@@ -2,7 +2,7 @@
// PSP FW Delivery Release Note
//
// Copyright 2016-2020, Advanced Micro Devices, Inc.
-// Date: Sep 17, 2020
+// Date: Oct 1, 2020
//----------------------------------------------------------------------------
Content:
@@ -10,17 +10,24 @@
This Build is compiled using the ARM license from the AMD license server.
Files:
- PspBootLoader_prod_RV.sbin [version: 0.8.A.7B] - PSP off-chip BootLoader (entry type 0x1), signed with production key
- PspRecoveryBootLoader_prod_RV.sbin [version: 0.8.A.7B] - PSP off-chip Recovery BootLoader (entry type 0x3), signed with production key
- secure_unlock_prod_RV.sbin [version: 0.8.A.7B] - PSP secure unlock (entry type 0x13), signed with production key
- psp_os_combined_prod_{RV, VG, VG12, VG20}.sbin [version: 0.8.A.7B] - PSP secure OS (entry type 0x2), signed with production key
- drv_sys_prod_{RV, VG, VG12, VG20}.sbin [version: 0.8.A.7B] - PSP system driver (entry type 0x28), signed with production key
+ PspBootLoader_prod_RV.sbin [version: 0.8.B.7B] - PSP off-chip BootLoader (entry type 0x1), signed with production key
+ PspRecoveryBootLoader_prod_RV.sbin [version: 0.8.B.7B] - PSP off-chip Recovery BootLoader (entry type 0x3), signed with production key
+ secure_unlock_prod_RV.sbin [version: 0.8.B.7B] - PSP secure unlock (entry type 0x13), signed with production key
+ psp_os_combined_prod_{RV, VG, VG12, VG20}.sbin [version: 0.8.B.7B] - PSP secure OS (entry type 0x2), signed with production key
+ drv_sys_prod_{RV, VG, VG12, VG20}.sbin [version: 0.8.B.7B] - PSP system driver (entry type 0x28), signed with production key
dr_ftpm_prod_RV.csbin [version: 3.26.0.4] - PSP fTPM (entry type 0xC), compressed and signed with production key
security_policy_RV1_FP5_AM4.sbin [version: A.2.3.2] - Raven1 APU Security Policy for Raven1 APU programs (entry type 0x24), signed with production key
security_policy_RV1_NPU_FP5_AM4.sbin [version: A.2.5.23] - Raven1 NPU Security Policy for Raven1 NPU programs (entry type 0x8024), signed with production key
security_policy_PCO_FP5_AM4.sbin [version: A.2.3.D2] - Raven1 APU Security Policy for Picasso APU programs (entry type 0x224), signed with production key
security_policy_RV2_FP5_AM4.sbin [version: A.2.4.26] - Raven2 APU Security Policy for Raven2 APU programs (entry type 0x124), signed with production key
+ver 0.8.B.7B
+PLAT-70669:[Chrome]: Update chromebook boot mode and opn info in pspbl oem app info structure
+PLAT-70668:[Chrome]: Introduce OEM app PSP BL info structure
+PLAT-70667:[Chrome]: Remove assert if booted on non-chromebook to boot on Mandolin
+PLAT-70666:[Chrome]: Testcase for PKCS#1 v1.5 based ModExp svc
+PLAT-70665:[Chrome]: Enable MODEXP SVC to OEM APP.
+
ver 0.8.A.7B
PLAT-70004:[Chrome]: Move the first IsPlatformChromeBook check after gAsicType is set
PLAT-69980:[Chrome]: Fix typo errors
diff --git a/picasso/PSP/PspBootLoader_WL_RV.sbin b/picasso/PSP/PspBootLoader_WL_RV.sbin
index 6c0077f..d2d43a5 100644
--- a/picasso/PSP/PspBootLoader_WL_RV.sbin
+++ b/picasso/PSP/PspBootLoader_WL_RV.sbin
Binary files differ
diff --git a/picasso/PSP/PspBootLoader_prod_RV.sbin b/picasso/PSP/PspBootLoader_prod_RV.sbin
index cce80b3..3bfa3f1 100644
--- a/picasso/PSP/PspBootLoader_prod_RV.sbin
+++ b/picasso/PSP/PspBootLoader_prod_RV.sbin
Binary files differ
diff --git a/picasso/PSP/PspRecoveryBootLoader_prod_RV.sbin b/picasso/PSP/PspRecoveryBootLoader_prod_RV.sbin
index 2d093e8..bdb365f 100644
--- a/picasso/PSP/PspRecoveryBootLoader_prod_RV.sbin
+++ b/picasso/PSP/PspRecoveryBootLoader_prod_RV.sbin
Binary files differ
diff --git a/picasso/PSP/SmuReleaseNotesPCO.txt b/picasso/PSP/SmuReleaseNotesPCO.txt
index e7f9520..5691a2b 100644
--- a/picasso/PSP/SmuReleaseNotesPCO.txt
+++ b/picasso/PSP/SmuReleaseNotesPCO.txt
@@ -48,7 +48,7 @@
| * Changelist
| - DXIO v31.445
| - [PLAT-61819] [IMP] CState-Boost is running in AVT when manual Overclocking in BIOS setup
-| - [PLAT-62205] [IMP] Set OC_ROLARITY_CONTROL cause other registers change in PORT_CONTROL_CNTR0
+| - [PLAT-62205] [IMP] Set OC_ROLARITY_CONTROL cause other registers change in PORT_CONTROL_CNTR0
| - [PLAT-64414] [IMP] MultiBitHitCause Exception in Embedded PCO Silicon
| * Files
| - /proj/smu_rel/smu10/picasso/picasso.rev4.30.73.0.zip
@@ -65,7 +65,7 @@
| * Changelist
| - DXIO v31.443
| - [PLAT-61732] [IMP] ComboAM4 1006 RC1 bad word
-| - [PLAT-62108] [IMP] UPEP Message 9 no response with reboot 1000 cycles, fail 1 of 20
+| - [PLAT-62108] [IMP] UPEP Message 9 no response with reboot 1000 cycles, fail 1 of 20
| - [PMFW-4210] [IMP] Allocate more space to extend section (reverted)
| - [PMFW-4653] [IMP] Disable PC6 wake interrupts during s0i3 resume until FCH is ready
| - [PMFW-4806] [IMP] Modifying external pcie FSDL to to avoid repetitive searching and message
@@ -84,7 +84,7 @@
| * Changelist
| - DXIO v31.443
| - [PMFW-4240] [UTB] EDC SOC Iddmax Vcn Cac value too large
-| - [PMFW-4179] [IMP] Initialize negative peak temperature after AGM clear table
+| - [PMFW-4179] [IMP] Initialize negative peak temperature after AGM clear table
| - [PMFW-4210] [IMP] Allocate more space to extend section
| * Files
| - /proj/smu_rel/smu10/picasso/picasso.rev4.30.71.0.zip
@@ -787,7 +787,7 @@
| - [PLAT-39590] [IMP] BIOS message to set Fit limit scalar
| - [PMFW-473] [NEW] GFX Fmax override
| - [PLAT-39812] [WKA] Modern Standby S0i3 FW TPM Error in Event Viewer / System Log
-| - [PLAT-39410] [IMP] Check MP2_FIRMWARE_FLAGS for MP2 handshake
+| - [PLAT-39410] [IMP] Check MP2_FIRMWARE_FLAGS for MP2 handshake
| - [PLAT-39702] [NEW] Modern Standby S0i3: SSID of LPC and SMBUS not save/restore
| - [PLAT-39349] [IMP] Add PostCode Level to CBS Option Enable SMU PostCode
| - [PMFW-519] [IMP] Update FIT Limits for 65W Config
@@ -997,13 +997,13 @@
| - [PMFW-224] [IMP] Add ACP Off to S0i3 Entry Condition (Improved)
| - [PMFW-228] [OPT] Picasso Should Lower the Core EDC CAC Scalar
| - [PLAT-36691] [UTB] NVMe Save/Rrestore for S0i3
-| - [PMFW-199] [ETB] Potential race condition for CGPG power status update
+| - [PMFW-199] [ETB] Potential race condition for CGPG power status update
| - [PLAT-36063] [IMP] S0i3 idle mask does not update to disregard USB
| - [PMFW-204] [IMP] Add IdleMask to PostCodes after S0i3 OsHint (Improved)
| - [PMFW-256] [IMP] Disable gfxoff race condition
| - [PMFW-205] [IMP] Add MP1 FW logging code into release
| - [PMFW-263] [IMP] Remove NVMe Save and Restore from S0i3
-| - [PMFW-15] [IMP] Park GfxClk into Bypass and turn off PLL when GfxClk Freq=200Mhz.
+| - [PMFW-15] [IMP] Park GfxClk into Bypass and turn off PLL when GfxClk Freq=200Mhz.
|
| * Files
| - /proj/smu_rel/smu10/picasso/picasso.rev4.30.22.0.zip
diff --git a/picasso/PSP/SmuReleaseNotesRV2.txt b/picasso/PSP/SmuReleaseNotesRV2.txt
index e2396aa..3ce7645 100644
--- a/picasso/PSP/SmuReleaseNotesRV2.txt
+++ b/picasso/PSP/SmuReleaseNotesRV2.txt
@@ -284,7 +284,7 @@
|
| * Changelist
| - DXIO FW version 31.433
-| - [PMFW-2122] [NEW] Support Dali 6W OPN
+| - [PMFW-2122] [NEW] Support Dali 6W OPN
|
+-----------------------------------------------------------------------------------------------------------
@@ -296,9 +296,9 @@
|
| * Changelist
| - DXIO FW version 31.433
-| - [PMFW-1801] [IMP] Fix release makefile to be consistent with source makefile
+| - [PMFW-1801] [IMP] Fix release makefile to be consistent with source makefile
| - [PMFW-2013] [WKA] VCN Video Encoding Voltage Marginality Issue in DC mode
-| - [PLAT-43640] [WKA] USB port reset fail after KB S3 resume, Yellow band in Device Manage
+| - [PLAT-43640] [WKA] USB port reset fail after KB S3 resume, Yellow band in Device Manage
|
+-----------------------------------------------------------------------------------------------------------
@@ -321,7 +321,7 @@
|
| * Changelist
| - DXIO FW version 31.429
-| - [PMFW-1739] [IMP] Move some codes to EXT section to create more TEXT space
+| - [PMFW-1739] [IMP] Move some codes to EXT section to create more TEXT space
| - [PMFW-1727] [WKA] USB YB when wake up system from S3 by KB behind USB HUB
|
+-----------------------------------------------------------------------------------------------------------
@@ -379,7 +379,7 @@
| * Changelist
| - DXIO FW version 31.425
| - [PMFW-1131] [NEW] Add Subprogram value to the FW Header
-| - [PMFW-1357] [OPT] Move feature disable fucntions to EXT_SECTION
+| - [PMFW-1357] [OPT] Move feature disable fucntions to EXT_SECTION
| - [PMFW-728] [OPT] Re-allocate .datatables space to .text section is reverted
|
+-----------------------------------------------------------------------------------------------------------
@@ -393,7 +393,7 @@
| * Changelist
| - DXIO FW version 31.425
| - [PMFW-1300] [NEW] Publsih BIOS/TEST messages to report overclocking capability
-| - [PLAT-43459] [ETB] GFX driver is not loaded after iGPU overclock in BIOS setup
+| - [PLAT-43459] [ETB] GFX driver is not loaded after iGPU overclock in BIOS setup
| - [PMFW-1230] [NEW] Add a PCD option to change AclkDpm0 from 200MHz to 400MHz
| - [PMFW-1313] [OPT] MP0CLK DS enable only for DC mode
|
@@ -407,7 +407,7 @@
|
| * Changelist
| - DXIO FW version. 31.425
-| - [PMFW-1263] [WKA] Discard CGPG enable if disable CGPG message is received during the delay
+| - [PMFW-1263] [WKA] Discard CGPG enable if disable CGPG message is received during the delay
| - [PLAT-43239] [WKA] R3-3200U Flavor 2 Processor USB 2.0 Device Recognized again after Safely removed by Windows Icon
|
+-----------------------------------------------------------------------------------------------------------
@@ -420,7 +420,7 @@
|
| * Changelist
| - DXIO FW version. 31.425
-| - [PLAT-41548] [ETB] FClk and UClk actual frequency ratio mismatch
+| - [PLAT-41548] [ETB] FClk and UClk actual frequency ratio mismatch
| - [PMFW-1114] [IMP] Rv2 Fw needs to be updated to v027 Sw document sync
| - [PMFW-1213] [NEW] Add SMU get message for current CCLK Fmax
| - [PMFW-1215] [ETB] Rounding min/max GFXCLK return values to neareset 10s
@@ -437,7 +437,7 @@
|
| * Changelist
| - DXIO FW version. 31.425
-| - [PMFW-933] [IMP] Reallocate space from scratch section to .isr_data section
+| - [PMFW-933] [IMP] Reallocate space from scratch section to .isr_data section
| - [PLAT-41596] [IMP] Publish OC messages to BIOS port
| - [PMFW-905] [IMP] System hang up when ping AP address for overnight (update)
| - [PMFW-909] [IMP] FUSE/Default Limits info of Power and Current required for Ryzen Master
@@ -453,7 +453,7 @@
|
| * Changelist
| - DXIO FW version. 31.425
-| - [PMFW-728] [OPT] Re-allocate .datatables space to .text section
+| - [PMFW-728] [OPT] Re-allocate .datatables space to .text section
| - [PMFW-701] [IMP] RV2 in PCO AM4: SMU Test Messages Required for Ryzen Master
| - [PMFW-726] [IMP] Enable continues data calculation when OC mode is enabled
| - [PLAT-41021] [IMP] Add fuse check for overclocking support
@@ -475,7 +475,7 @@
| * Changelist
| - DXIO FW version. 31.423
| - [PLAT-40266] [WKA] Move PCTL0_MISC programming to SMU for secure policy update
-| - [PMFW-699] [IMP] Raven2x FP5: Bypass Precision Boost Overdrive (PBO) Implementation
+| - [PMFW-699] [IMP] Raven2x FP5: Bypass Precision Boost Overdrive (PBO) Implementation
|
+-----------------------------------------------------------------------------------------------------------
@@ -488,7 +488,7 @@
| * Changelist
| - DXIO FW version. 31.422
| - [PMFW-599] [IMP] PSI0 Workaround Code Cleanup
-| - [PMFW-600] [IMP] Put PeAPM Code in EXT_SECTION
+| - [PMFW-600] [IMP] Put PeAPM Code in EXT_SECTION
| - [PLAT-39838] [IMP] Add USB31 OVERCURRENT_MAP_1_CNTR0
| - [PMFW-623] [NEW] Add Managed Overclocking
|
@@ -705,7 +705,7 @@
| * Changelist
| - DXIO FW version. 0.332
| - [PLAT-29635] [IMP] SMU USB Firmware programming for LLUCTL and GRXTHRCFG
-| - [SMURVN2-48] [UTB] Resource protect DispClk change.
+| - [SMURVN2-48] [UTB] Resource protect DispClk change.
| - [SMURVN2-49] [IMP] Fix system hang issue when OS tries to boot with PLL_POWER_DOWN disabled.
| - [SMURVN2-50] [IMP] Increase precision for voltages in AGM.
| - [SMURVN2-51] Fixed issue GPU0 PLL not powered down after S3 resume.
@@ -806,7 +806,7 @@
|
| * Changelist
| - DXIO FW version. 0.328
-| - Corrected fclk fcstate setting for case switch from BYPASS to DFS.
+| - Corrected fclk fcstate setting for case switch from BYPASS to DFS.
| - bypass MP2 reg access in ACPI (workaround)
|
+-----------------------------------------------------------------------------------------------------------
@@ -860,7 +860,7 @@
| - Added LivMINVid and LinMinEnable fuse
|
+-----------------------------------------------------------------------------------------------------------
-
+
+---------------------------+
| Version 37.2.5 |
+---------------------------+-------------------------------------------------------------------------------
@@ -910,7 +910,7 @@
| - Integrated changes from RV1x up to CL2773697
| - Updated USB related function to new IP. USB watermark setting for LPDDR4 retraining is still outstanding.
| - Updated UMC related register settings for LivMin and LPDDR4 retraining.
-| - Fixed pmfw_fastsim.sv to be synced with pmfw_fastsim.h and scratch_info.h in RV2. We need to variantize pmfw_fastsim.sv for FF and RV2 in the future.
+| - Fixed pmfw_fastsim.sv to be synced with pmfw_fastsim.h and scratch_info.h in RV2. We need to variantize pmfw_fastsim.sv for FF and RV2 in the future.
|
+-----------------------------------------------------------------------------------------------------------
@@ -921,16 +921,16 @@
| 31/03/17
|
| * Features enabled
-| - LPDDR4 retraining (preliminary)
+| - LPDDR4 retraining (preliminary)
| - RLC PACE (preliminary)
|
| * Changelist
| - Integrated changes from RV1x up to CL2726404
-| - Included preliminary version of LPDDR4 retraining. Handling ZQCAL and USB watermark during
+| - Included preliminary version of LPDDR4 retraining. Handling ZQCAL and USB watermark during
| memory retraining is still outstanding.
| - Included preliminary version of RLC PACE feature
-| - Code update for clocks change in RV2, include FCLK change, 2 slices of CLKB/CLKC and 2 DROOP detectors only.
-| - Minor code update for 2 cores only (core 1 and core 3)
+| - Code update for clocks change in RV2, include FCLK change, 2 slices of CLKB/CLKC and 2 DROOP detectors only.
+| - Minor code update for 2 cores only (core 1 and core 3)
|
+-----------------------------------------------------------------------------------------------------------
@@ -945,8 +945,8 @@
|
| * Changelist
| - Integrated base code from RV1 and compiled them under RV2 environment.
-| - Implemented preliminary version of Long Idle vMIN feature. For LPDDR4 system,
-| one caveat is that ConvertD2toPhyLp3 bit in UMC has not been set before entering LIVMIN.
+| - Implemented preliminary version of Long Idle vMIN feature. For LPDDR4 system,
+| one caveat is that ConvertD2toPhyLp3 bit in UMC has not been set before entering LIVMIN.
| - Gated off unused/bypassed DFS slices.
|
+-----------------------------------------------------------------------------------------------------------
diff --git a/picasso/PSP/drv_sys_prod_RV.sbin b/picasso/PSP/drv_sys_prod_RV.sbin
index aedbf7b..2527e8d 100644
--- a/picasso/PSP/drv_sys_prod_RV.sbin
+++ b/picasso/PSP/drv_sys_prod_RV.sbin
Binary files differ
diff --git a/picasso/PSP/psp_os_combined_prod_RV.sbin b/picasso/PSP/psp_os_combined_prod_RV.sbin
index 5342f07..a8a7ac6 100644
--- a/picasso/PSP/psp_os_combined_prod_RV.sbin
+++ b/picasso/PSP/psp_os_combined_prod_RV.sbin
Binary files differ
diff --git a/picasso/PSP/secure_unlock_prod_RV.sbin b/picasso/PSP/secure_unlock_prod_RV.sbin
index ec9f624..ed97ec3 100644
--- a/picasso/PSP/secure_unlock_prod_RV.sbin
+++ b/picasso/PSP/secure_unlock_prod_RV.sbin
Binary files differ
