)]}'
{
  "commit": "2cf1f3c426847f5d6d4b872d415eaa654c384cfa",
  "tree": "52841ca75176933c9cbe40ac149b5c7a4eb3c0a7",
  "parents": [
    "2d7cf1e6e2ad74afa25d65043ff978cebef92837"
  ],
  "author": {
    "name": "Tim Wawrzynczak",
    "email": "twawrzynczak@chromium.org",
    "time": "Wed May 15 14:42:20 2019"
  },
  "committer": {
    "name": "chrome-bot",
    "email": "chrome-bot@chromium.org",
    "time": "Thu May 23 14:35:03 2019"
  },
  "message": "UPSTREAM: soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.\n\nWhen FSP UPD parameters are configured, also configure the GSPI CS lines\nappropriately.  GSPI driver assumes CS0 is the CS signal to use.\n\nBUG\u003db:130329260\nBRANCH\u003dNone\nTEST\u003dBoot Kohaku, TPM communcation still functional.\n\nChange-Id: Ib5f410e0688d6e75aa9f6532375019b6fe98182c\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nOriginal-Commit-Id: ddbf2c4af05b5cbd889d6a55e67734c8a041bc66\nOriginal-Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c\nOriginal-Signed-off-by: Tim Wawrzynczak \u003ctwawrzynczak@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791\nOriginal-Reviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nOriginal-Reviewed-by: Paul Fagerburg \u003cpfagerburg@chromium.org\u003e\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/1619902\nCommit-Ready: Patrick Georgi \u003cpgeorgi@chromium.org\u003e\nTested-by: Patrick Georgi \u003cpgeorgi@chromium.org\u003e\nLegacy-Commit-Queue: Commit Bot \u003ccommit-bot@chromium.org\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@chromium.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cc01d10fe81683812a45610f41ce0ec4c036d32d",
      "old_mode": 33188,
      "old_path": "src/soc/intel/cannonlake/fsp_params.c",
      "new_id": "dd9388296d7cb4327e31120938983d7586b6a1ce",
      "new_mode": 33188,
      "new_path": "src/soc/intel/cannonlake/fsp_params.c"
    }
  ]
}